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Crossing Over

Lattice Introduces MachXO

When I was a kid, my Dad had a big’ol vacuum-tube audio amplifier. It was massive, heated the room, and took several minutes to “warm up” before it was ready for duty. Sometimes the transformers would hum along with the music, which was OK if the tune was in a key that was a multiple of 60Hz. To me, the thing seemed a bit clunky compared with the transistor-based mainstays of the day. When I asked Dad about the amp, he’d always reply “Well, son, they used to make them all that way, but it got too expensive.”

Dad had a soft spot for the Dodo birds of technology. He was nostalgic for the era of aesthetic over-engineering and lamented the loss of beautiful but impractical designs of the past. He was much more knobs and meters than pushbuttons and digital readouts – a musician with a mechanical engineering degree for whom form did not always follow function. Together we watched the quiet demise of the points-and-condenser ignition, the 8-track tape, the rotary dial telephone, and many more.

Now we are all spectators at the dawn of the extinction of the CPLD. It’s a bit of a stretch to imagine that something as obscurely pedestrian as a programmable logic device could foster a fan following, but Lattice’s MachXO architecture announcement last week gave me that familiar feeling nonetheless. Unlike rival Altera with their Max II “CPLD” family, Lattice doesn’t pretend that their new MachXO device is a CPLD, even with a nod and a wink. While XO walks, talks, quacks, performs and prices like our familiar product-term friend, under the architectural hood lie the LUTs and interconnect of a non-volatile FPGA.

Clearly the time has come when the most efficient way to implement the features required in a high-end CPLD are not with a CPLD at all. It’s a simple matter of math. As my Dad would say, “It got too expensive.” Now, the newly introduced MachXO is poised at the price/performance nexus between the current low-cost FPGA and high-end CPLD markets. They bring the efficiencies of FPGA to the users of CPLD. Even though the devices are intended to be priced, marketed, and used in the traditional way, they are implemented in 130nm non-volatile Flash technology with a 4-input LUT architecture.

For those wanting a CPLD, MachXO has instant-on, non-volatile, low-power, high-speed operation. For those looking for a small, super-cheap FPGA, MachXO offers low standby power, embedded block RAM, and PLL clocking, with PCI and LVDS I/O. Similar to their recently announced XP FPGA family, MachXO also offers a transparent logic update/reconfiguration feature called TransFR. This feature allows a complete reconfiguration to be loaded into on-chip flash memory while the device is operating normally with the old configuration, then the new configuration can be activated in milliseconds while keeping all I/Os in a well-behaved state.

Because of the use of flash technology, block RAMs can also function as ROM which can come in handy for functions like product licensing, security, and serializing. Supporting the family’s expected popularity in bridging applications, dedicated “hard” FIFO capability is included which improves performance and efficiency of FIFO implementation without using up precious LUTs. Additionally, a “sleep” mode takes the device down to near-zero power consumption for use in power-sensitive applications.

Lattice announced immediate availability of the MachXO256 and MachXO640 devices (with 256 and 640 LUTs respectively) and the family is slated to include 256, 640, 1200 and 2280 LUT devices with user I/O counts ranging from 78 to 271. Pricing will be in the expected range for CPLDs with family members starting in the low single-digit range in volume. Lattice also continues to nobly buck the industry norm of super-early announcements by rolling out the family with some devices already available for shipment.

Lattice is clearly in a transition phase as a company. Despite challenging times with their business over the past few years, they have managed a steady stream of new product announcements over the past 18 months, each with a clear niche and compelling differentiation. MachXO helps shore up Lattice’s defenses on one of the company’s staples, CPLD devices, where competitors have been gradually turning up the heat.

Most of the recent new product announcements from Lattice have been FPGAs, and now that their CPLDs are beginning to be FPGAs as well, it appears that the company will at long last complete its successful transition from CPLD-centric supplier to serious competitor in the faster-growing FPGA market. Because Lattice’s CPLD history has involved them in a number of high-volume applications, they have a potential sales channel advantage selling to the high-volume market that is emerging as the hottest growth area in FPGA. Applications like automotive, consumer, medical, computer and networking are migrating to programmable logic in droves, and the company with the right mix of marketing technology and timing stands to make significant gains.

Still, I’ll miss the CPLDs when they’re gone. Even though staring wistfully at a scrawny square on an old cold circuit board could never match the warm glow of the vacuum tube amp pumping out Tony Mottola through the Voice of the Theater speakers, there may be some alternative aesthetic longing for the conceptual elegance of sparse arrays and wide product terms that we’ll never be able to experience again

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