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Deeply Embedded

ESC 2005 - the FPGA View

Last year we pointed out that the embedded systems conference (ESC) was being quietly taken over by FPGAs. Booth after booth on the tradeshow floor boasted boards with programmable logic devices prominently displayed. The trend continued this year with even more programmable presence amidst a host of announcements bringing FPGAs more to the center of the embedded systems stage and, conversely, embedded applications to the forefront of the FPGA world.

All of the FPGA vendors had a presence this year, and booths were bustling with activity. FPGA Journal was on-hand to take in all the action, distill it down, and distribute it back to you in the form of insightful answers to your burning questions. We’ve asked the questions for you (we are a full-service publication) and given our best responses based on information we gathered at the event. We’ve also awarded “coolest” and “most interesting” titles to several items based strictly and arbitrarily on our personal opinion.

Question 1 – Who had the coolest booth?

 Our coolest booth award goes to Wind River. In fact, their ESC booth wins the award for the coolest booth we’ve seen in the past two years of trade shows. Parked preemptively in front of the main entrance, Wind River’s cubic monolith towers to an altitude that would only fit in the highest section of the exhibit hall. Gigantic sculptured letters “D S O” (for Device Software Optimization) line the right side of the booth (pointed strategically toward the Microsoft booth). Inside each letter are “embedded” video presentations which are viewed by looking through small ports on the side. The theme, reminiscent of “Fight Club” emphasized the anarchist origins of the open source movement. Wind River wants to make the point that they are now the open source, multi-OS, standards-based company.

Honorable mention goes to Atmel for their skybar, or guard tower, or … whatever it was. Their booth featured an innovative second-story balcony overlooking the show floor and giving them an excellent vantage point to watch the flow of curious embedded attendees.

Question 2 – What was the most interesting announcement?

Good question. Every tradeshow offers a flurry of new- and revised-product announcements as well as announcements of alliances and partnerships. From an FPGA perspective, the most intriguing announcement was the newly formed partnership between ARM and Actel. Actel has been going ever more head-to-head with the two dominant FPGA suppliers, beginning with their ProASIC (now up to ProASIC-3) assault on the low-cost, high-volume, value-based FPGA market. Now, they’re showing that they have no intention of sitting on the sidelines while programmable devices move into the starring role in embedded systems. Coming to the party on the arm of ARM, we’re betting that they’ll attract a lot of attention from the ARM-strong embedded software crowd, most of whom are much more comfortable with the well-known ARM brand than with the (to them, at least) vagaries of leaders and followers in the FPGA space.

The details of the ARM/Actel relationship are not clear yet, but expect to see Actel devices with available ARM cores in production within a year. That means you’ll probably be able to develop software using your old familiar development tools, debuggers, and ARM-compatible RTOS and middleware and target a low-cost, non-volatile Actel ProASIC-3 device.

Also in the exciting partnership department, Xilinx and AccelChip are teaming up to deliver a high-performance, end-to-end solution for digital signal processing (DSP) design. AccelChip’s Matlab-to-gates design flow for DSP blocks (AccelChip DSP Synthesis) now offers smoothly into Xilinx’s System Generator for DSP tools. With AccelChip DSP Synthesis version 2005.1 you can automatically generate a verified System Generator IP block based on a MATLAB model. With this model, you can use the Mathworks’s Simulink for cycle-accurate simulation, and synthesize your block down to hardware all within the System Generator environment. The AccelChip/Xilinx alliance is a smart move for both companies as it creates a compelling and complete DSP design flow with significant value in the integration.

If you’re interested in more general acceleration of computation, Xilinx is also announcing the 7.1 release of their Platform Studio suite for embedded design with FPGAs. With this announcement, Xilinx is touting the automated integration of user-defined hardware co-processors. Xilinx’s auxiliary processing unit (APU) controller creates a general-purpose hardware interface for hardware accelerators tied to custom instructions in their embedded PowerPC405 processors. The new Platform Studio simplifies the process of adding custom instructions and connecting the accelerators for those instructions through the APU controller.

On the Altera side of the house, they’re bringing multi-processor development using multiple Nios II cores into the spotlight. Nios II has been announced for about a year now, and is picking up steam right where its predecessor (Nios) left off. Altera has been extremely successful in the configurable soft-core processor arena due both to the efficient and flexible architecture of their Nios processors, and because of the clean, simple, interface of their SOPC Builder embedded design suite.

While soft cores are inherently slower than their hard-optimized counterparts, they are much more versatile in their configurability, and in theory, you can use as many as needed to handle the processing load of your system. The tricky part of multiple processors, of course, is partitioning your application into parallel processes and coordinating the communication channels between them. Altera announced a partnership with Lauterbach to provide multi-processor debug support for multiple Nios II processors operating in Altera FPGAs or HardCopy structured ASICs. Lauterbach’s TRACE32-PowerDebug module uses a JTAG connection to the FPGA to provide multi-core debugging and control. The system allows Nios II processors to be logically grouped and synchronized giving simultaneous start, step and break commands.

Question 3 – What were the most interesting trends?

We were hoping you’d ask that one. While the infusion of FPGA hardware into the embedded systems community is certainly a compelling continuation of the trend we noted last year, this year’s most striking trend has to be the sudden ubiquity of Eclipse. In the space of a couple of years, Eclipse taken over the hearts and souls of embedded software developers and tool providers. Once highly proprietary and closed, Wind River has made a major philosophy switch and now openly embraces the open-source paradigm. As one treks the aisles at ESC, the Eclipse moniker is everywhere, from Wind River to Mentor’s Accelerated Technology, and even including FPGA companies like Xilinx and Altera. Eclipse is an open source, extensible development platform for building software. Eclipse includes support for modeling, language development environments, testing and performance, business intelligence, client applications and embedded development. A global collection of technology companies, universities and research institutions develop and support the Eclipse Platform.

Second was the trend toward general convergence of hardware platforms. While FPGAs, Structured ASICs, Digital Signal Processors DSPs, and conventional processors are extremely diverse in their origins, technology and industry trends are pushing all these technologies toward some virtual point of convergence. FPGAs started as almost purely programmable fabric, but have since added embedded processor cores, sophisticated I/O capability, memory, hard-wired multipliers and dedicated peripherals to increase their versatility as embedded platforms. Structured ASICs (whose origins are unquestionably gate-arrays) look almost identical to FPGAs in their hard-IP offering, differing only in the programming method for the configurable fabric. DSPs now typically have embedded control processors, sophisticated I/O, memory, dedicated DSP arithmetic hardware, and exclusively software programmability.

We had an interesting chat with Gene Frantz, Principal Fellow at Texas instruments, where he pointed out that DSPs and conventional processors are becoming virtually identical in feature sets, differentiated mainly by their handling of interrupts and their marketing literature. Expanding on his point, when viewed through embedded systems goggles, all these technologies are morphing into similar single-chip software-programmable embedded platforms with processors, memory, I/O, and peripherals. The primary distinguishing trait of each remains the amount and type of support for custom hardware configurability or re-configurability. It is in that battleground that both the consumers and producers of these devices will attempt to differentiate themselves and their technologies over the longer haul.

 Question 4 – What was the coolest demo?

This one was a split decision. In general, split decisions from a single judge might be considered signs of schizophrenia, but in this case we feel confident in our ambiguity. National Instruments was demonstrating their newest FPGA-based version of LabVIEW FPGA. This is one of those products that is so versatile and powerful, it’s almost difficult to understand at first reading. With LabVIEW FPGA, NI has provided a hardware/software conduit that allows you to custom design a graphical user interface (GUI) that will run on a variety of computing platforms, and create a high-performance, FPGA-based, two-way interface between that GUI and almost any arbitrary piece of hardware. Obviously designed with the control and data collection needs of test and measurement, LabVIEW FPGA is so generic that its potential uses go far beyond T&M.

Co-winner of our coolest demo award goes to Memec/Insight for their Mini-module system. If you’ve been reading FPGA Journal for long, you know that it’s becoming increasingly challenging to smoothly integrate your favorite FPGA onto your circuit board. Memec has a handy piece of hardware with the job already done for you. The mini-module is a daughterboard containing a Xilinx Virtex-4 or Spartan-3 device and associated peripherals and configuration hardware that plugs atop a connector-rich development board. When you’re done developing, you can un-plug it from there and drop the daughterboard into a more permanent residence in your prototype, or even early-production system. All the small-geometry board-layer-intensive work is done for you on the mini module (which really is quite mini – about the size of your thumb). The daughterboard can then be plugged into a regular garden-variety PCB of four layers or so, making the addition of an FPGA-based embedded computer to your system a much simpler task.

Question 5 – Why wasn’t I at the conference?

 Only you can accurately answer this one for yourself, but we do have some observations. The venerable conference/tradeshow is somewhat of a dinosaur in the internet age. It’s hard to justify (on purely technical or educational grounds) the cost of a trip to a tradeshow when any information you might collect there is readily available online, for free, at your desk. Apart from the ability to actually burn your finger on an FPGA development board, there is less information available at any vendor’s booth than can be easily accessed on their website. Paper presentations rarely offer any insight (other than quiet amusement at watching untrained introverts nervously confront public speaking) that one can’t pick up from careful reading of papers and proceedings. Panel sessions, usually mostly populated with employees of the vendors represented on the panel, normally digress into unresolved bickering over competing corporate technical philosophies, or passionate pseudo-religious wars over speculatively academic topics that have little relevance in current industry.

Why then, do we go? First (you can conveniently cut here if you’re forwarding the first part of this article to your boss), it’s a boondoggle. Conferences are still the best way to get an all-expenses-paid semi-vacation at someplace you don’t live, where you can travel by air, stay in a nice hotel, dine at quality restaurants, and pick up free useless trinkets to take home to your kids. Second, you attend conferences so you can network. By “network” we mean get some quality face-time with your future employer. If you’re feeling stagnant in your current job, there’s no better way to sample the greener grass on the other side of the fence (and to look for inviting ways to cross) than attending a tradeshow. Third, and as a final bonus, there are often some nice parties.

Here’s our suggestion to get the best of both worlds. Get your corporate approval for the trip. Drop by registration the first day to get your badge and pick up the all-important proceedings and party guide. Next, go out and have a good time. When you get home, page through the papers to see if you missed anything, then cut-and-paste excerpts from the FPGA Journal summary into your trip report. We promise not to tell.

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