feature article
Subscribe Now

Making the Jump to 10G

There is a radical shift in the beliefs about high speed serial feasibility as it moves beyond 3 Gbps on up to 10 Gbps. In a matter of few short years, the industry has gone from saying “impossible” to the concept of 10 Gbps with existing CMOS NRZ signaling to today, where all the required productized elements are in place for delivering manufacturable systems operational anywhere from 2.5 to 10Gbps. These components include: off the shelf transceivers, backplanes and connectors.  The reason for this shift has been a concerted, partnered effort by all parties including semiconductor vendors, backplane, connector manufacturers and signal integrity experts. Moving beyond 3 Gbps was not going to happen just by having super connectors or ultra high speed silicon or exotic materials. A strong coalition between all the players mentioned above has moved the entire industry forward.

Xilinx has not only found itself in the middle of this transition, but also played an integral role in it. Central to emergence of key technologies such as high speed transceivers, standardized backplanes and connectors has been the availability of advanced, high performance 2.5 to 10Gbps transceivers integrated into a highly digital, programmable environment such as the Xilinx Virtex™-II Pro X/ Virtex-4 FPGAs. With the wide availability of such devices, high speed serial is now available to every digital designer building systems today. FPGAs with serial I/O have created a tipping point for serial I/O. No longer is high speed serial the domain of a few who could afford to develop custom chips, backplanes and connectors in order to achieve their performance targets.

Looking back at the path traversed to get to where we are today, from the year 2000 where bold predictions about optical 10G backplanes were made, to the year 2003, the industry was attacking the problem by seeking to independently improve each of the individual elements. Gradually, as engineers started working on solving the challenges, they initially focused on high performance backplanes with exotic materials and connectors. As soon as these components were manufactured, designers realized that connectors and materials are not always the limiting factors and good design practices can actually enable the use of mainstream materials and connectors. Once this became clear, the cost associated with building 10G became less of a factor. As a result, most of the mechanical layer elements and capability for building 10G systems are in place today.

The other inflection point in this scenario was the availability of high speed transceivers capable of driving 10G signaling. Only a few such devices were available, most likely custom, and based on technologies other than CMOS. Multi-level signaling techniques other than standard NRZ were also being proposed. But substantial investments in evaluating the actual potential of multilevel signaling showed that, in fact, it could not actually deliver the imagined performance. Additionally, using such devices was extremely cost prohibitive to build 10G systems, and further presented interoperability issues. In the meantime, 10G transceivers emerged based on a standard CMOS process using NRZ signaling in an off-the-shelf part such as the Virtex-II Pro X FPGA. This provided the strong and timely boost needed to cross this barrier as well. All of the conceptual 10G systems now became reality as Xilinx, working in concert with other manufacturers, demonstrated Virtex-II Pro X driving 10 Gbps across all major backplanes and connectors over the last year.

As a result, from the end of last year, most major backplane and connector vendors either have announced or will be announcing backplane and connector products that can be manufactured today. Historically, in any industry, once standardization occurs around any standard or milestone, the cost of building products or systems around that standard nosedives. This is for 10G systems as well – as the costs have gone down with the availability of standardized components, the industry is now poised to make the jump to 10G with ease.


Leave a Reply

featured blogs
Aug 18, 2018
Once upon a time, the Santa Clara Valley was called the Valley of Heart'€™s Delight; the main industry was growing prunes; and there were orchards filled with apricot and cherry trees all over the place. Then in 1955, a future Nobel Prize winner named William Shockley moved...
Aug 17, 2018
Samtec’s growing portfolio of high-performance Silicon-to-Silicon'„¢ Applications Solutions answer the design challenges of routing 56 Gbps signals through a system. However, finding the ideal solution in a single-click probably is an obstacle. Samtec last updated the...
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...