feature article
Subscribe Now

What’s Time to a Pig?

FPGA at the End of 2004

The efficiency expert stopped several mornings in a row on his commute into the city, pulling his car onto the shoulder of the road alongside the farm with the small apple orchard. He watched in amazement, even getting out his binoculars to be sure, as the farmer carefully lifted a full-grown pig out of the pig pen, carried him down the path to the orchard, and then climbed the small step-ladder, lifting the pig over his head and waiting patiently while the pig ate a few apples from the tree. The farmer then returned the pig to the pen, picked up another sow and schlepped her down to the orchard to feed. The spectacle continued for over an hour until all the pigs had been fed and the farmer was obviously exhausted.

Professional curiosity eventually won out, and the efficiency expert decided to confront the farmer about his process. One morning he put down his binoculars, climbed through the fence, and met the farmer as he finished his feeding ritual. “Don’t you see how much time you’re wasting, and how much faster it would be if you picked the apples and brought them to the pigs in the pen?” The farmer shrugged and stared at the stranger with slight suspicion. Finally, he responded with a question of his own: “What’s time to a pig?”

Although the story has been around for awhile, it still applies this year in the programmable logic industry. When evaluating engineering options, it is particularly easy for project managers and engineers alike to underestimate the importance of time to market and to overlook technologies, tools, and IP that can get them to the finish line faster. FPGAs have long been known as the time to market champions, but otherwise reasonable design teams still often dismiss them, citing outdated myths about inadequate performance, insufficient density, and excessive power consumption. Here at the end of 2004, most of those deficiencies have been addressed well enough to make programmable logic an attractive option for a wide variety of applications, but the legacy of previous generations persists in the perceptions of many, causing them to choose inferior alternatives with longer lead times. Let’s take a look at the major FPGA-related events of 2004 and see if we can find a faster way to feed the folks waiting for our new designs to hit the market.

Low Cost FPGA

Grab your pig and let’s head for the cheap end of the orchard. If anything, 2004 was the year of the low-cost FPGA. In 2003 we began this foray into FPGAs for the masses, but 2004 saw these miserly devices move firmly into the mainstream. Xilinx staked its claim early by putting their super-low-cost Spartan-3 series up first on the 90nm line. With 90nm Spartan-3 on the market throughout 2004, Xilinx was the first company with a significant volume ramp on the new process node. Altera followed, announcing Cyclone II, the 90nm successor to their highly successful Cyclone series. Lattice Semiconductor jumped into the game from the FPGA sidelines by forming a foundry partnership with Fujitsu, and launching the first of a series of new FPGA families aimed at the high-volume, low-cost market. Lattice’s new EC and ECP series integrate features found on many high-end FPGAs into a cost optimized offering that is designed to give the two industry leaders a run for their money.

Don’t make the mistake of thinking that the low-cost race is low-stakes, though. Since FPGAs got their start in a relatively small but elite high-margin market, the low-cost, high-volume game is an enormous opportunity for programmable logic companies to expand into new areas. The competition for new sockets in application areas such as consumer electronics and automotive is bound to be ferocious. The largest players in the industry are looking to low-cost as a way to expand and diversify their customer base, and the smaller silicon suppliers see a discontinuity that might allow them to beat the big boys out of some market share. The movement of programmable logic technology into so many diverse markets all at once is bound to create opportunities for new niche suppliers to sneak in as well if they pick specific problems and focus on solving them best.

Digital Signal Processing (DSP) Acceleration

Most FPGA companies will tell you publicly that FPGAs peacefully co-exist with traditional DSP chips in many systems, and that they’re not out to steal market share from suppliers like TI that have made a franchise out of the specialty high-performance devices. Nevertheless, when you look at these “peaceful” programmable devices grazing happily in their printed circuit board pastures alongside their DSP cousins, you might notice a few wolf ears poking out from their sheep suits. When you look at the datasheet and see triple-digit numbers of optimized, hard-core multipliers and multiply-accumulates, it becomes difficult to fully embrace the peaceful co-existence line. It’s pretty hard to imagine that those embedded blocks are intended for anything short of massively parallel acceleration of high-performance DSP algorithms.

If you want to point fingers here, you’ll need all of them. Xilinx, Altera, and Lattice all have high-performance DSP blocks on their current devices (even in the low-cost families). Actel has also fired a warning shot across the bow with recent announcements of DSP-specific IP blocks, and the handwriting is on the wall with a number of silicon startups eyeing the DSP problem as well.

As we’ve said many times, tools are the bottleneck in DSP on FPGA, and a number of companies like AccelChip, Catalytic, Celoxica, and Mentor Graphics continued to press forward in 2004 with increasingly advanced techniques for turning algorithms into high-performance parallel hardware, and FPGA synthesis leader Synplicity joined the race with an impressive DSP synthesis tool of their own. Several of these companies have made significant progress on the fundamental problem of generating a parallel architecture to realize an algorithm that was conceived in a sequential language. Simultaneously, these commercial solutions are beginning to address more of the problems surrounding the core such as providing a robust IP library for DSP designers, and addressing the challenge of floating- to fixed-point conversion for moving from software-based algorithms to hardware architectures.

Embedded Systems on Programmable Devices

In both the low-cost and traditional programmable logic markets, the advent of embedded processors in FPGAs was a key element in the 2004 story. Altera and Xilinx both saw widespread acceptance of their soft-core RISC processors Nios (and Nios II) and MicroBlaze. Xilinx also saw increased adoption of their PowerPC hard-core processor in their Virtex II-Pro families, and is continuing to offer it in some versions of their new Virtex-4 platform. Both vendors continued their usual stream of superfluous superlative claims regarding adoption and success of these platforms, but looking through the hype with our truth-seeking goggles, there is actually a significant trend toward applications that use FPGAs as systems-on-chip, replacing what would have previously been ASIC sockets.

As a result, watch over the next year for an explosion in companies providing tools, IP, and support for the embedded-on-FPGA market. Already companies like Altium, Celoxica, Mentor Graphics’ Accelerated Technology, First Silicon Solutions and many more are betting heavily on the trend. New entries like Impulse Accelerated Technology and Poseidon Design Systems are also waiting in the wings to attack this emerging opportunity.

The soft-processor trend started innocently enough a few years ago as an effort to provide simple micro-controllers to replace complex state machine implementations in sequential designs. Designers began to see additional potential, however, and FPGA companies raced to provide more capable processing capability in soft-core form. Soft processors are particularly attractive because of the potential to customize them for each application, and because with their relatively small footprint it is easy and inexpensive to set up a multi-processor environment on a single chip.

If we switch our truth-seeking goggles to future-vision mode, we can see the unmatched potential of FPGAs as ultra-high performance reconfigurable computing machines of the future. Customized soft-core processors working in parallel with hardware accelerators (generated with tools such as those being refined in the DSP arena) have computing performance potential that far exceeds the capabilities of Von Neumann architecture machines. Interestingly, the hardware and IP for this are basically in place today. The element that is missing is the complex, unified compilation environment that could take ordinary software and automatically optimize it for a multi-processor/hardware accelerator platform.

Structured ASIC

2004 also saw structured ASIC pull itself up and take its first few baby steps on wobbly legs in the market. In previous years, structured ASIC was primarily a topic for editors, researchers and venture capitalists. This year, however, several vendors including LSI and NEC claimed a significant number of commercial wins, and enough design starts to give some validation to the structured ASIC approach. Structured ASIC technology is primarily viable today because of a gap in density between the largest FPGAs and mainstream cell-based ASICs. Like any market opportunity that relies on a gap, structured ASIC is particularly vulnerable to simultaneous attack from both sides. In response, FPGA vendors are attacking the fledgling structured ASIC market from multiple angles. Xilinx is offering EasyPath versions of their high-end FPGA devices, allowing FPGAs to be used essentially “as-is” but at ASIC-like prices. Altera is pushing ahead with their HardCopy program which creates an actual mask-programmed ASIC directly from your FPGA design with minimal NRE and schedule impact. These efforts will likely keep the other structured ASIC vendors chasing densities above what FPGAs currently offer.

There are also a number of alternative technologies emerging around structured ASIC such as those offered by eASIC and LeopardLogic. These companies seek to capture some of the flexibility advantages of FPGAs in combination with performance, density, power and cost characteristics of ASICs. As cell-based ASICs become increasingly less attractive at future process nodes, we should see more innovation in alternative architectures like these. It will also be interesting to watch which application areas begin to gravitate toward these solutions. These companies’ choice of target market for their technology will probably determine whether they move forward into the mainstream, grow modestly in niche areas, or are marginalized by competitors with more mainstream approaches.

In the structured ASIC tools market, however, there seems to be a bit of a runaway. Betting on the growth potential of the emerging technology, and seeing the natural fit of their easy-to-use approach to EDA technology, Synplicity got an early start in the structured ASIC tools game and is now almost the only player on the field. They have a compelling offering with their tool suite, and have done an excellent job forging the critical relationships with the silicon suppliers that are required to dominate their part of the market. If structured ASIC truly takes off in the next couple of years, watch for Synplicity to grow with it.

Alternatives to SRAM FPGA

Even in the FPGA market itself, the status-quo was being questioned in 2004. Altera asserted that FPGAs make better CPLDs than CPLDs do with their new Max II CPLD line which is essentially a flash-based FPGA. Actel continued their long-term strategy of touting the benefits of non-volatile technologies over SRAM in areas like security, reliability, total system cost, and power, and QuickLogic went full-steam into the low-power side of the market with their Eclipse II line of antifuse-based devices.

On the architecture front, Altera challenged the long-standing notion that the 4-input look up table (LUT) was the optimal FPGA architecture by introducing their variable-width cell in Stratix II. Meanwhile, market leader Xilinx attacked the prevailing trend to pile more and more general purpose hard IP on large FPGAs with their more diverse Virtex-4 architecture which offers varying mixes of hard IP features targeted at different types of applications.

90nm

Also in 2004, a small number of our pigs have evidently begun to fly themselves to the orchard to feed. Despite the pessimistic predictions of the skeptics and naysayers, 90nm is now definitely in volume production at Xilinx, and Altera is probably not far behind. Much like the megahertz race in PCs, however, the continuous push of programmable logic to the next process node is likely to lose the attention of the majority of the audience. With increasingly diverse demands being placed on FPGA technology by a wide variety of applications, fewer and fewer incremental needs are addressed by simple inertia down the path of Moore’s Law. To win tomorrow’s customers, silicon vendors will need the right mix of IP, features, and tools. The three big “Ps” of today: performance, power, and price, are likely to become the small “Ps” of tomorrow with other, more specific requirements taking the spotlight.

The fourth “P”, programmability, is the one that is likely to continue to deliver what more design teams need. Over the long haul, time to market is the most valuable advantage an implementation technology can provide. With the complexity of systems continually on the rise, programmability is the single most important capability in both speeding products to market, and keeping them viable in the field for a longer time. As more design teams come to grips with that reality in 2005, the future of FPGAs and other programmable platforms is bright. Will this apply to your projects as well? Just remember to keep a lookout on the road near your farm for a friendly stranger with binoculars. He might have some helpful advice.

7 thoughts on “What’s Time to a Pig?”

  1. Pingback: orospu
  2. Pingback: engineering
  3. Pingback: Dokter anak banten

Leave a Reply

featured blogs
Aug 17, 2018
Samtec’s growing portfolio of high-performance Silicon-to-Silicon'„¢ Applications Solutions answer the design challenges of routing 56 Gbps signals through a system. However, finding the ideal solution in a single-click probably is an obstacle. Samtec last updated the...
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...