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Cost-Reduction Quagmire

Structured ASIC and Other Options

Your design is working perfectly – on your development board.

Unfortunately, your company is probably not planning to ship FPGA development boards as part of their product. You’ll have to come up with something a little more practical and cost effective if you’re going to win “employee of the decade” when your skunk-works design ships one million units.

There is general consensus, even among ASIC suppliers, that FPGAs are the highest productivity platform for getting your design debugged and running in actual hardware. If you have an idea, and you want a hardware implementation of that idea as quickly as possible, nothing will get you there quicker (or cheaper) than downloading a set of FPGA tools, buying a development board with the required device, I/O, and peripherals, finding a reference design that looks something like what you’re trying to build, hooking up some good-quality IP cores, and writing VHDL or Verilog for any missing pieces. I have confirmed this repeatedly, with design team after design team, in almost every conceivable application area.

Recently (at Denali’s MemCon, actually), I listened to a panel session debating the relative merits of FPGAs and structured ASIC. The panel featured representatives from major FPGA and structured ASIC companies, and it took almost no time for the panel to agree on what we already stated. Everyone should start his or her system design with FPGAs. The interesting part of the debate was what followed, and the answers were (as in any public discussion between parties with a stake on opposite sides of the issue) quite obscured by FUD-injected marketing rhetoric. (For those of you who haven’t taken a course in confrontational marketing recently, “FUD” stands for fear, uncertainty, and doubt – generally directed toward whatever your competitor is offering.)

Let’s say you agreed with these panelists and got your design working correctly on one or more FPGA development boards. Now you want a strategy to go to production with the best possible solution. Here are the big-picture choices and some situations where you might want to consider each one.

Solution 1: Cost-optimized FPGA

The first solution to consider is a cost-optimized FPGA. These devices have appeared on the market during the past two years or so, and have some very compelling benefits. You should consider these devices if several conditions are true. First, your design has to fit on one. If it’s too big for a single device, your economics are blown and you should probably look for a different solution. Second, as with any FPGA-based solution, it should fit your power/performance budget.

The advantages of a cost-optimized FPGA are many. Price-wise, these components can be had for low double-digits, and some even for single-digit unit cost. They are clearly the time-to-market champs, particularly if you have already used one in your development process. Because they are usually field-reprogrammable, they are also the most forgiving solution. If you design in field upgradeability, you can ship the early version of your product, confident that you can release a new bitstream later to upgrade or fix any problems discovered after shipment.

If you want to go down the low-cost FPGA path even farther, think about ways you can leverage the unique features of these devices in your design. Reprogrammability is not just a safety net to minimize the cost of upgrades and engineering changes. If your design is modal, you may be able to re-configure the FPGA for each mode, allowing you to get away with a smaller part in production. If you ship variants of your design for different markets or geographies, a programmable part can allow you to serve all your customers with a single hardware configuration, varying only the FPGA programming. If you want to execute a complicated algorithm in a hurry, an FPGA-based reconfigurable computing engine can far outperform any similar-cost processor.

Speaking of processors, you can have one of those too. Or even more than one if you like. With embedded soft-core processors as sophisticated as 32-bit RISC machines now dropping into even the low-cost FPGA lines, you can have a system-on-chip for the price of peanuts. Beware, though. If you design one of these proprietary puppies into your programmable logic prototype, you’re pretty well wedded to the FPGA solution for life.

If you don’t believe that these are going to be popular products, just look at the slew of semiconductor companies jumping into the fray. After success with their first-round Spartan and Cyclone lines, Xilinx and Altera are both off to round two with new 90nm offerings in the super-cheap space. Xilinx is now in volume production with its 90nm Spartan 3 with over 1 million devices shipped, and Altera is expecting to start volume deliveries of 90nm Cyclone II soon. Lattice is leveraging their low-cost CPLD experience and their new fabrication agreement with Fujitsu with their newly released EC and ECP lines, and Actel is positioning their ProASIC Plus offering directly against the super-saver SRAM families as well.

Actel’s approach is interesting in that their flash-based FPGAs make different tradeoffs from their SRAM competitors. As you might expect, the flash solutions don’t have the Fmax performance of their counterparts, but if they run fast enough for your application, that’s all that counts. Because they are semi-statically configured, they don’t require extra configuration circuitry that can amount to a significant chunk of your budget when dealing with low-cost FPGAs. They also are more miserly with quiescent power than their SRAM-based rivals.

Solution 2: High-end FPGA Conversion

If you spent a lot more on your development board (Did you have to get a 3rd level manager’s signature to buy it?), and the device(s) mounted on it have a word like “Virtex” or “Stratix” written on them, you probably can forget the low-cost FPGA approach. If took advantage of the wonderful capabilities of these devices, you also locked yourself out of the simple solution of value-based FPGA. If you are a black-belt designer who can optimize architectures with one hand while juggling chainsaws with the other, you might try squeezing your design into one of the price-optimized programmable platforms. Otherwise, we need to explore other answers.

Both of the largest FPGA vendors have cost-reduction solutions, and their approaches are quite different. Xilinx has the lowest-impact plan possible with their EasyPath solution. With EasyPath, Xilinx works with you to set up a custom test program to verify FPGAs for your specific design. Once the program is in place, they’ll sell you custom-tested FPGAs at a substantial discount.

How do they accomplish this? As we know, an FPGA is really just a special case of a big RAM. In RAM devices, we’re accustomed to the fact that not every bit in a production device is perfect. Logic that compensates for a single bad transistor is built in and the end product never knows or cares that there was a dust particle on the chip. FPGAs can work the same way. If one look up table (LUT) out of tens of thousands on the device doesn’t work, you can simply verify the FPGA with designs that don’t use that LUT. This is what EasyPath’s custom testing accomplishes. It verifies that each device you buy passes with your design and your test vectors. Portions of the logic that you don’t use are not tested.

The only catch is that you cannot count on the device to be fully reprogrammable. If you use a different design, you might stray into logic cells that were not tested with your original test program, and the results could be bad. Xilinx does offer specific, limited reprogrammability with EasyPath devices, but you need to be sure you stay within the specified boundaries.

The advantages of EasyPath are substantial, once you understand the limitations. Since the device you’re buying actually is an FPGA, there is absolutely no modification required. Package footprint, pinout, IP, performance, power – everything is identical to your FPGA prototype because you’re still using the same FPGA. The cost savings is generated by the yield, manufacturing, and test flow. Because there is little to no re-engineering required on Xilinx’s part, you also can usually get EasyPath versions of the latest devices immediately after the FPGA family is available.

Altera’s HardCopy is a direct-to-structured-ASIC solution. They have fabricated structured ASIC devices from their popular high-end FPGAs that are a 1:1 mapping. Once you have your FPGA-based solution working, Altera will convert it directly into a mask-programmed version of the same product architecture. The advantages of this approach are that you get a true, mask-programmed device with corresponding performance improvement, power reduction, and single-chip benefits. Compared with other structured-ASIC options, the conversion from FPGA prototype is the simplest, since the device architecture is essentially the same, and all your Altera IP is directly compatible.

The tradeoffs, compared with the Xilinx EasyPath solution, are that you do incur the cost and schedule impact of having masks made, you have to alter your design somewhat to account for the fact that it’s no longer an SRAM FPGA, and you may not have access to the latest FPGA architectures, as delivery of the HardCopy version of a new device family is bound to lag somewhat, since Altera has significant engineering work to do to create a HardCopy equivalent of a new FPGA family. This effect can be seen today, in fact, as Xilinx has already announced the EasyPath version of their latest Virtex 4 family, while Altera has not yet announced a HardCopy version of its latest Stratix II family, even though Stratix II was announced before Virtex 4.

A number of vendors and design houses also offer FPGA migration services that can convert your FPGA design into a gate array or other mask-programmed technology. This path is more expensive and effort-intensive than either of the afore-mentioned vendor-supplied migrations, but it warrants consideration in some cases. If you have a design that doesn’t cleanly fit one of the established cost-reduction paths, and you don’t want to jump into full-blown structured ASIC (which isn’t a very difficult leap, actually) you might want to find out more about conversion/migration services.

Solution 3: Structured ASIC

If that prototyping board of yours has more than one of those expensive FPGAs on it (You really did need that third-level manager signature, didn’t you?), you probably want to think about the full-blown structured ASIC option. Structured ASICs offer a number of advantages compared with high-end FPGA, particularly when compared with cell-based ASIC solutions. They have very low unit costs, high density and performance, short turnaround, low NRE, ASIC-like power consumption, and FPGA-like tool costs.

While structured ASICs have been offered for a couple of years, most of the market hasn’t figured out what to make of them yet. The reason for this is probably that the structured ASIC vendors’ marketing departments are running a little behind the curve. They have a good excuse. The companies that make structured ASIC products made their real money from cell-based ASIC lines. With FPGA companies eating into their profits from the bottom, they rolled out structured ASIC lines in retaliation. Their natural instinct, then, was to position these products directly against the evil programmable devices that were attacking them.

The problem with that positioning is that structured ASICs make a much more compelling solution when compared with cell-based products. Since most structured ASIC lines’ lowest density is close to the highest density available in FPGA, there really isn’t much overlap between single FPGAs and single structured ASICs. A structured ASIC is a good replacement for a two-or-more FPGA system, but the one-to-one replacement isn’t often an option. Against cell-based designs, however, structured ASICs are stellar. They have much shorter design cycles, an order of magnitude lower NRE, much lower design tool costs, significantly less expertise required for success, and very competitive performance, density, power, and unit cost. The marketing mavens at these companies are understandably reluctant to launch an all-out assault on their own revenue generators, however, so they have put together campaigns that probably confused the customer more than they promoted this very compelling technology.

A number of reputable ASIC vendors are offering structured ASIC solutions. NEC Electronics has breached the 90nm threshold with their latest ISSP offering. ISSP90 is NEC’s second-generation structured ASIC offering, following on the heels of their .15-micron ISSP1. NEC is targeting high-end consumer devices such as digital cameras and recording systems that need the combination of low unit cost, high performance, and low power dissipation offered by these devices. Like other structured ASIC vendors, NEC has made a priority of generating a smooth design flow. They bundle a complete set of design tools with the NRE, so you don’t have to put together your own ASIC tool suite, and you don’t have to spend $500K per engineer for EDA tools before you start.

LSI logic is making a bold bet with their RapidChip structured ASIC line. RapidChip has a well-tested and structured design flow, a wealth of available IP, and compelling advantages in unit cost, performance, and power over both cell-based and programmable logic alternatives. LSI has taken an approach similar to Xilinx’s Virtex 4 and Altera’s Stratix and Stratix GX, by offering a variety of pre-configured IP variants, which they call “slices”. Their “Integrator” versions are cost-optimized and bare-bones for integrating large amounts of high-performance logic at the lowest cost. Their “Extreme” series offers goodies like SerDes I/O for those applications that need cutting-edge IP. If you want to use embedded processors, LSI’s landing zones allow cores like ARM or MIPS processors to be dropped in with minimal integration hassle.

LSI’s RapidWorx tool set integrates industry-leading solutions customized specifically for RapidChip technology. This means, again, that you don’t have to have industrial-strength (and high-cost) ASIC tools to get the job done. LSI has carefully qualified the tool flow for success, and your design cycle and investment will shrink significantly as a result.

LSI also offers a migration path to full cell-based ASIC similar to the FPGA vendors’ FPGA cost reduction options. If your design is in high volume and might go to super-high volume, a smooth move to cell-based optimality would be a wonderful option.

Tooling and IP

Caveat Designor! OK, that probably isn’t proper Latin, but the sentiment is true. If you follow the typical FPGA path of least resistance, and use the FPGA vendor-supplied tools and IP, you will save money up front, but you also severely limit your cost reduction options. If you did your FPGA design completely with the proprietary tool set and maybe even dropped in a RISC core for good measure, you’re pretty well committed to staying with that vendor for your cost reduction, even if the technology match is not optimal.

It costs more up-front, but if you use a vendor-neutral tool suite and portable IP, you leave yourself in a much more flexible position when your design bursts into high-volume production due to your clever and insightful design work. As a third-party EDA supplier, Synplicity is in a unique position as the dominant provider of both FPGA and structured ASIC solutions. Their FPGA tools are widely regarded as providing excellent results on every FPGA vendor’s technology and allowing the greatest degree of design portability between vendors. If you decide to move your FPGA design to structured ASIC, Synplicity’s tools are built-in to almost every structured ASIC vendors signoff tool flow. Some structured ASIC vendors’ tool suites even include Synplicity’s synthesis and physical synthesis products as standard parts of the solution.

Take a Bow

As you step to the podium to give your rousing Employee-of-the-Decade speech, remember what got you there. In addition to perfectly identifying the customer’s pain and providing an elegant, well-engineered solution, you planned ahead and made your design easy to cost-reduce by your clever selection of IP, tools, and the appropriate cost-reduction silicon platform. Check back often, though. The rules of the game are changing as fast as vendors of cell-based ASIC, structured ASIC, and FPGA can maneuver around their competitors’ solutions in a race to capture the lion’s share of what will likely be the most lucrative segment of the semiconductor market.

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