feature article
Subscribe Now

Low Cost Leapfrog

New FPGAs Jump into the High Volume Arena

Imagine watching a professional sports contest (let’s say a basketball game), starting sometime in the middle. In this particular game, there is no visible scoreboard. You watch one team score, then the other. Each seems to be making progress and amassing points, but without a scorecard, you really have no way to tell who’s winning or losing.

There were two exciting announcements in the emerging low-cost, high-volume FPGA market this week. The key issue in this contest is, of course, price. Unfortunately, amidst the flurry of features, claims and specifications, price is the one thing that’s almost impossible to nail down precisely. Each company explains details of the new features, capabilities, and design elements, with strong assurances that these will all add up to more of the kind of gates you need for less money than their competitors charge.

Now, back at our basketball game, suppose you took matters into your own hands and went down to ask one of the teams how they were progressing. Then suppose they gave you an answer like “By halftime in this game, we’re pretty sure we’ll have about 50 points.” When you went to ask the other team how they were doing, they’d reply “…well, as of 10 minutes ago we had 21 points…” While both of these tidbits may be informative and accurate, they really give you no more insight as to who’s winning the game.

As long as both teams are scoring, though, you know that points are being racked up for somebody. In the case of low-cost FPGAs, that can only be good news for the customers. No matter who’s ahead, the contest is heating up and competition improves the breed. This week, the competitive spotlight is on Lattice and Altera with their new lines of low-cost programmable penny-pinchers.

First up (and first with samples available) is Lattice Semiconductor with their new Lattice-EC and Lattice ECP-DSP families. Delivering on the expectations they set a couple of months ago with their newly-announced Fujitsu fab agreement, this is clearly a breakthrough announcement for Lattice. These are highly-competitive products targeted at a new, rapid growth market where the playing field is much more level than in the traditional FPGA space. While Lattice has worked to make their presence known in FPGA before, they have primarily succeeded in the CPLD market. This announcement represents their best effort by far to field a competitive FPGA offering.

Low-cost market segments like consumer electronics have not traditionally made extensive use of FPGAs. They have, however, used large volumes of CPLDs, so Lattice’s experience selling CPLDs to that market will help them with their new FPGA line. While other vendors have ground their teeth deciding whether or not to put high-performance hard-wired multipliers on their low-cost devices, Lattice decided to offer both flavors and let the customer choose. The ECP-DSP line (“Economy Plus DSP”) includes DSP blocks that can implement up to 36X36 multipliers and 18X18MACs, as well as summation and pipelining for those wanting DSP functions in their low-cost FPGA. The EC (“Economy”) line is cost-optimized without the multipliers for those who just want the most gates for their buck.

The new lines are based on Fujitsu’s Low-k, copper, 130nm CMOS process and use a 1.2V power supply. The devices are optimized for small die-size which should give them very competitive pricing, even compared with 90nm offerings (which are still suffering from shrinking pains as the kinks are ironed out of the process).

In the spirit of reducing total system cost, Lattice has designed the new family to be configurable by low-cost SPI flash devices. Lattice claims that this can offer 4 times lower cost per bit than proprietary boot PROMs. The density range of the new family is from 1.5K to 41K (4-input) LUTs. The devices are offered in low-cost packages including TQFP, PQFP and fpBGA in pin counts from 67 to 576.

Lattice’s press release gives specific pricing information, but take note – different vendors give pricing based on different volumes and different delivery dates. (Remember our basketball game?) Don’t compare prices for 250K volume in mid-2005 with Lattice’s 1K volume in mid-2004. Pricing varies with both volume and date as new processes come online and yields improve, so be sure you’re comparing apples to apples.

Next up this week Altera is also raising their bid in the low-cost arena. Altera is announcing a 90nm sequel to their wildly successful “Cyclone” line. “Cyclone II” offers higher density and lower cost than its predecessor and keeps Altera in a strong position in the econo-race as well. Altera claims the new family will be 30% lower cost than Cyclone and will offer 3X the density.

Altera prefaces the announcement of the new family with a history of the commercial successes of the original Cyclone line, and the list is impressive. With examples such as prosumer video cameras, GPS, fish-finders, wireless networking, digital TV, and consumer PC video products, Altera is showing that the storm of FPGA technology into the consumer arena has definitely begun, and Altera products are in it.

While everyone knew that price/density curves would drop to the point that overall time-to-market advantages and NRE savings would make FPGAs compelling options for consumer applications, these devices are making innovative use of reprogrammability in ways that render them clearly superior to ASIC implementations for these products. Pinnacle Systems effectively triples the density of the FPGA by reconfiguring it with one of 3 different bitstreams depending on the operating mode of their MovieBox Deluxe. In addition, they configure the device from a bitstream embedded in Windows drivers, so they are almost immune to hardware design errors as they can offer hardware patches and upgrades to existing customers via a simple download.

The Cyclone II family, scheduled for sampling in early 2005, is designed to surf the coming tsunami of high-volume, low-cost FPGA sockets with maximum efficiency. In addition to the size and cost advantages, Cyclone II will offer 4X the memory of Cyclone and includes up to 150 embedded 18X18 multipliers. The devices also include dedicated DDR2 and QDRII interface circuitry to connect to state-of-the-art external memory with 668-Mbps performance. Internal clock speeds are rated at 250MHz which is more than enough for most mainstream applications. In addition, the new device supports Altera’s Nios II soft-core processor making Cyclone II a super-low-cost embedded system design platform.

Unlike rival Xilinx (who started their 90nm rollout with their low-cost Spartan 3 family), Altera went to production first with its flagship Stratix II line, then based their low-cost offering on the same process. This should mean fewer skinned knees and bruised elbows as they fight their way into production with the new line. Also, by releasing their low-cost 90nm offering after the competition, they had a known target, so they are able to differentiate themselves without guessing.

Cyclone II, which is based in TSMC’s 90nm, low-k process, is scheduled for first delivery in February 2005 with the EP2C35 device. Additional family members are supposed to be in place by the second half of 2005.

The addition of these latest Lattice and Altera lines heat up an already hotly contested low-cost logic derby being fought by Xilinx’s Spartan 3, Altera’s Cyclone, and Actel’s ProASIC Plus families. This is a serious business with serious stakes, and we should watch for more entries in the coming months as vendors plan their strategies in this emerging and lucrative logic market.

Who’s going to win? Well, a scoreboard would certainly be nice right now, wouldn’t it? Unfortunately, with the primary indicator, (price for a given feature mix at a given volume on a given date,) still up in the air, it will be hard to say for awhile. For now, you’ll have to carefully evaluate your needs including feature set, delivery dates, and production volume, against the available offerings and make your decision from there. It will also pay to re-evaluate your options often as this market is destined to change rapidly, and most of the changes will be in your favor.

Leave a Reply

featured blogs
Apr 25, 2024
Structures in Allegro X layout editors let you create reusable building blocks for your PCBs, saving you time and ensuring consistency. What are Structures? Structures are pre-defined groups of design objects, such as vias, connecting lines (clines), and shapes. You can combi...
Apr 24, 2024
Learn about maskless electron beam lithography and see how Multibeam's industry-first e-beam semiconductor lithography system leverages Synopsys software.The post Synopsys and Multibeam Accelerate Innovation with First Production-Ready E-Beam Lithography System appeared fir...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Digi XBee 3 Global Cellular Solutions
Sponsored by Mouser Electronics and Digi
Adding cellular capabilities to your next design can be a complicated, time consuming process. In this episode of Chalk Talk, Amelia Dalton and Alec Jahnke from Digi chat about how Digi XBee Global Cellular Solutions can help you navigate the complexities of adding cellular connectivity to your next design. They investigate how the Digi XBee software can help you monitor and manage your connected devices and how the Digi Xbee 3 cellular ecosystem can help future proof your next design.
Nov 6, 2023
22,627 views