I have now attended more than half of the 41 annual Design Automation Conferences. One of the things I’ve noticed during those twenty-odd years is that DAC started at the end of the design flow and moved forward. From the days when the hot topics in design automation were replacing tape and glass with Calma systems, the focus of DAC has been subjects closest to silicon. This, in turn, set the tone for the attendees as DAC’s content pushed its way from implementation details at the transistor level toward higher levels of design abstraction.
The difficult thing about levels of abstraction above RTL is that they require a new and more diverse audience. While the semiconductor design flow for almost all implementation fabrics is similar from RTL on down and appeals to designers with a common set of skills and expertise, the land above RTL is more varied and domain-specific. DSP designers need a way to go from abstractions such as MATLAB to RTL. Embedded systems designers want to partition C and C++ code into software and hardware threads that can execute on multiple processors and hardware accelerators. There are almost as many vocabularies, design languages, and methodologies as there are application domains. By and large, tools working in these upper-echelons of the design flow would be used by designers that handed off their finished work to DAC attendees.
It is exciting, then, to see higher levels of design abstraction emerge as one of the biggest themes at DAC this year. While RTL has been the standard starting point for DAC’s delights in years past, this year there was a significant trend toward increased abstraction. As FPGAs move toward greater capability and flexibility with the introduction of embedded soft processors and DSP-specific multipliers and MAC blocks, programmable logic may become the gateway to hardware design for a new group of applications developers from diverse backgrounds. This DAC showed that, even if those people don’t come to this particular trade show, their tools will be waiting for them when they arrive.
Since there is typically a lot of coverage of what the big EDA vendors are doing at DAC, we thought we’d take a look at some of the more edgy offerings from the middle of the tradeshow floor. Here’s what we saw that might be interesting and applicable in FPGA and programmable logic.
Heading up the high-level design hierarchy is veteran Celoxica. Celoxica has solutions targeted at the embedded systems designer, and recognizes both the software-biased background of their customers as well as the emerging trend away from virtual prototyping and toward hardware-in-the-loop (HIL) design methods. Celoxica, now surprisingly the seasoned veterans in the C software synthesis field, was touting its new SystemC support at DAC. Celoxica is also astute in offering a hardware development board along with their solutions showing that they are aware of the emerging trend toward hardware-based design and debug, and they want to provide their customers a turnkey design solution with no missing major components.
Newer to the embedded processing space is CriticalBlue whose Cascade tool takes the approach of generating optimized co-processors as accelerators. Cascade analyzes the instructions used in a portion of an application and generates a co-processor optimized to execute those instructions efficiently. The tool generates synthesizable RTL for the co-processor that can be synthesized by downstream tools such as Synplicity’s Synplify Pro and Synplify ASIC, and it is also compatible with Cadence’s Incisive functional verification platform.
Aiming at the DSP delegation are AccelChip, and more recently Synplicity. As we’ve discussed in previous articles, both these companies offer solutions for the DSP designer seeking hardware acceleration. In the case of AccelChip, the flow starts with MATLAB’s M language and moves to silicon. Synplicity’s newly announced Synplify-DSP product begins one step later in the process with MathWorks’ Simulink as the head of the flow. AccelChip’s approach is to do the floating-to-fixed point conversion for you and automatically synthesize an optimized datapath. Synplicity’s solution is based on using a set of pre-configured blocks in MathWorks’s Simulink tool, then generating RTL for synthesis with Synplify. Both tools aim to significantly reduce the learning curve for traditional DSP designers working their way from off-the-shelf DSP processors into custom hardware. This is a key problem to solve as the design complexity barrier is the only thing separating DSP designers from orders of magnitude performance, cost, and power improvement available with FPGAs.
As discussed in our previous “Catapult C” article, Mentor Graphics was abuzz at DAC with customer testimonials from designers trying out the idea of algorithmic design. Mentor claims that designing at a truly algorithmic level (with untimed C or C++ source code) gives designers the flexibility to make powerful architectural trade-offs before committing to an RTL representation.
Also joining the higher-abstraction hierarchy is Bluespec who announced their SystemVerilog-based tools for high-level design of ASIC and FPGA. Bluespec works from a high-level language model to deliver cycle-accurate C for system verification as well as RTL for synthesis and implementation. Bluespec’s source is SystemVerilog with the addition of assertions to control the generated architecture. The tool is based on an MIT technology called “Term Rewriting Systems.”
With all these new languages and levels of abstraction racing around, there is also a race to integrate them into simulation environments. FPGA-savvy Aldec has gone to great lengths to produce an environment that allows easy integration of a variety of languages and abstractions into a single simulation and debugging environment.
Startup SpiraTech was also touting technology for integrating multiple levels of abstraction and different languages with a plug-and-play transaction-level integrator that connects simulators dealing with multiple languages at varying levels of abstraction. SpiraTech’s “Cohesive Transformer” includes a graphical multi-level viewer that shows cause-effect relationships between multiple levels of abstraction as it coordinates the execution of multiple, simultaneously operating simulators.
This is but a brief sampling of the vendors we visited. As we discussed in our “Winds of Change” article, the big news at the DAC show almost always comes from the small booths as innovative startups seek to prove themselves worthy of adoption and acquisition by the stodgier stalwarts of the industry. This year’s crop was a good one and reflects renewed vigor in a recently lackluster industry.
These companies are all offering new technologies that should be useful and applicable to FPGA design. If you’re elevating beyond the standard RTL-to-FPGA design flow, you might want to check out some of their offerings.