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Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Achieving Fast Formal Verification in Highly Configurable Design Environment

Sonics is a trusted leader in on-chip networks, which connect all components of a system. Since failure of an on-chip network leads to failure of the SoC, Sonics spends considerable time verifying its configurable IP. When Sonics began looking into formal verification, the company quickly turned to Cadence's JasperGold® verification apps. In this video, Drew Wingard, the company's co-founder and CTO, explains how the algorithms, as well as the packaging of those algorithms, made it easy for RTL developers to be productive quickly with formal verification, even in their highly configurable design environment.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Sigrity PowerSI Tackles SSO Noise: Customer Success Story

AEI Systems needed to perform a worst case SSO analysis to screen their design and verify that defects and deficiencies would be eliminated prior to test, production and delivery. In doing so, they found that Cadence Sigrity PowerSI was the only tool tested that was able to provide the close correlation to the actual measurement needed to validate the RTAX board example. Click to see the process and results AEI Systems saw using Sigrity PowerSI to successfully evaluate worst case SSO noise.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Tips for Creating Effective Hybrid Virtual Prototypes

Creating a virtual prototype becomes more challenging when graphics cores are involved because they have different instruction sets than CPUs. Watch this video to hear Robert Kaye, technical specialist with the Development Solutions Group at ARM, share tips and techniques for creating hybrid virtual platforms with the Cadence® Palladium® XP platform and accelerated verification IP.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

chalk talks

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

IP and Process Solutions for Energy-efficient PMICs

In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.

Integrated Design Environment for FPGA

Do you find that FPGA design flows can get a bit confusing and difficult to manage? What we really need is an integrated design environment that will help us keep our design activities organized. In this episode of Chalk TalkHD Amelia chats with Satyam Jani from Aldec about integrated design environments (IDEs) for FPGA design, why FPGA designers need a vendor-independent IDE, and how an FPGA-centric IDE can help us get through our design flow quite a bit more easily.

High Speed Data Acquisition and Software Defined Radio Made Simple

Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk TalkHD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

latest papers and content

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

UltraScale + 16nm Technology and Portfolio Backgrounder

Learn about new memory, 3D-on-3D, and multi-processing SoC (MPSoC) technologies introduced in Xilinx’s new 16nm UltraScale+™ portfolio of FPGAs, 3D ICs and MPSoCs, collectively delivering a generation ahead of value for next generation systems. This backgrounder describes the innovations introduced in the Kintex®, Virtex®, and Zynq® UltraScale+ families and how they address a broad broad range of next generation applications, including LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT) applications.

Achieving Fast Formal Verification in Highly Configurable Design Environment

Sonics is a trusted leader in on-chip networks, which connect all components of a system. Since failure of an on-chip network leads to failure of the SoC, Sonics spends considerable time verifying its configurable IP. When Sonics began looking into formal verification, the company quickly turned to Cadence's JasperGold® verification apps. In this video, Drew Wingard, the company's co-founder and CTO, explains how the algorithms, as well as the packaging of those algorithms, made it easy for RTL developers to be productive quickly with formal verification, even in their highly configurable design environment.

Tips for Creating Effective Hybrid Virtual Prototypes

Creating a virtual prototype becomes more challenging when graphics cores are involved because they have different instruction sets than CPUs. Watch this video to hear Robert Kaye, technical specialist with the Development Solutions Group at ARM, share tips and techniques for creating hybrid virtual platforms with the Cadence® Palladium® XP platform and accelerated verification IP.

Zynq UltraScale+ MPSoC Overview

Building on the industry’s first All Programmable SoC, Xilinx is enabling a generation ahead of integration and intelligence with unprecedented levels of heterogeneous multi-processing system on chip and delivering 5X system-level performance per watt. By combining the right engines for the right tasks, Zynq® UltraScale+™ MPSoC provides a flexible, scalable processing platform with the highest levels of security and safety.

Introducing the 16nm UltraScale+ Families

Xilinx’s 16nm UltraScale+™ family of FPGAs, 3D ICs and MPSoCs, combines new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies, delivering a generation ahead of value. The Xilinx UltraScale+ FPGA portfolio is comprised of Xilinx’s market leading Kintex® UltraScale+ FPGA and Virtex® UltraScale+ FPGA and 3D IC families, while the Zynq® UltraScale+ family includes the industry’s first all programmable MPSoCs. Optimized at the system level, UltraScale+ delivers value far beyond a traditional process node migration – providing 2–5X greater system level performance/watt over 28nm devices, far more systems integration and intelligence, and the highest level of security and safety.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Saving Routing Resources, Speeding Up Timing Closure at Freescale Semiconductor

Routing and timing closure were big challenges on the high-performance cores developed by Freescale Semiconductor. How did the engineers improve these processes? Watch this video to hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence® Encounter® digital implementation tools to save routing resources and speed up the timing closure process.

How Real Number Modeling Improves Functional Verification for Mixed-Signal SoCs

Functional verification is particularly challenging for mixed-signal SoCs. In this 3-minute video, Dushyant Juneja, a CAD engineer at Analog Devices, talks about early bug detection and more thorough functional verification of the company's mixed-signal and low-power designs. The company achieved this by applying advanced methodology based on real number modeling and simulation in Cadence® Incisive® Enterprise Simulator.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

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more on demand

Debug This! Class-based testbench debugging with Visualizer

Rich Edelman says class-based debug is good news because it is not the same as debugging RTL. You don’t have to be an object-oriented programmer in order to debug a class-based testbench. Such a testbench just a bunch of objects – some statically created, some dynamic – which interact with the DUT. The upshot? Class based debug doesn’t have to be hard!

Design Data Management with PTC Windchill and Cadence Allegro PCB

Learn how PTC and Cadence have developed a unique collaboration environment to connect Allegro PCB design data with the Windchill PLM system for robust file management and check-in check-out capabilities.

National Instruments Comments on Xilinx Extensible Processing Platform

Xilinx Extensible Processing Platform testimonial from customer National Instruments.

I/O Design Flexibility with the FPGA Mezzanine Card (FMC)

The FPGA’s inherent flexibility has proven indispensable for the creation of external I/O interfaces. However, unless I/O is implemented on a daughter card (mezzanine module), replacing the physical I/O components and connectors requires changing the FPGA board design. To avoid these costs, designers have historically relied on the PCI™ Mezzanine Card (PMC) and Switched Mezzanine Card (XMC) standards. The problem is that these were developed years ago for general purpose solutions such as single-board computers— not FPGAs.

Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesday video, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.

CircuitSpace 5.0: Discover Why Design Reuse Has Never Been Easier or More Flexible

This webinar is designed for Hardware Engineers and PCB Designers requiring an easy to use, flexible, and comprehensive design reuse methodology to coexist with their current OrCAD and Allegro PCB design tools. It is intended for new users as well as current users of EMA CircuitSpace software and focuses on front-to-back reuse methodologies and incorporates the new and enhanced features of version 5.0. Learn how the CircuitSpace 5.0 feature set can expedite your PCB layout process.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

Sigrity PowerSI Tackles SSO Noise: Customer Success Story

AEI Systems needed to perform a worst case SSO analysis to screen their design and verify that defects and deficiencies would be eliminated prior to test, production and delivery. In doing so, they found that Cadence Sigrity PowerSI was the only tool tested that was able to provide the close correlation to the actual measurement needed to validate the RTAX board example. Click to see the process and results AEI Systems saw using Sigrity PowerSI to successfully evaluate worst case SSO noise.

Reduce Verification Complexity in Low/Multi-Power Designs

The increasing demand for highly reliable products covers many industries, all process nodes, and almost all design implementations. To satisfy this demand, reliability requirements are growing in all market segments.Accurate and repeatable reliability verification is now a critical capability, both for advanced nodes and for increasingly complex products being produced at established nodes. Read more of this whitepaper to learn how to create an easy-to-use, automated verification solution for low-power and multi-power domain designs.

Leveraging Power Leadership at 28nm with Xilinx 7 Series FPGAs

In this new whitepaper, learn the most effective methods for minimizing FPGA power consumption with Xilinx's industry-leading power solutions. Real-world design examples showcasing Xilinx power estimation and optimization methods are discussed.

From Simulation to Emulation – A Fully Reusable UVM Framework

This paper introduces an acceleration-ready UVM framework and explains why it is needed and how to create it. Readers will learn how to write block-level UVM environments that can be reused directly in emulation for block, subsystem, and system level verification. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include ARM AMBA 4, ARM AMBA 5, OCP, DDR, LPDDR, LPDDR3, LPDDR4, Wide I/O, Wide I/O2, DRAM, eMMC, eMMC5, UFS, CSI-3, SoundWire, USB, PCIe, and SSIC.

See How Customizable Processors Can Help to Offload Your Apps Processor

In this week's Whiteboard Wednesday video, we take a little different approach and show you a fun and fast way to understand how Cadence® Tensilica® Xtensa® processors work, and how you can easily use them to offload your applications processor. After the video, learn more about Xtensa processors at http://bit.ly/1xZfYdP.

Drive the Automotive Market with a Distinct Advantage: Xilinx Automotive Spartan-6 FPGAs

Just about 10 years ago, you could count on one hand the number of electronic systems in an automobile. Today, it is difficult to find a single system in a car that isn't electronic or at least electromechanical, as car manufacturers look beyond engine block size and body design to electronics to differentiate their offerings. Xilinx(r) Automotive (XA) Spartan(r) FPGAs are playing an increasingly important role in this auto electronics revolution.

SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors fabric behavior, and the Interconnect Workbench for performance analysis. The combined solution delivers functional verification along with latency and bandwidth analysis to fine-tune interconnect performance.


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