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Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Enabling High-Speed Radio Designs With Xilinx All Programmable FPGAs and SoCs

This white paper describes the capabilities of Xilinx® 7 series All Programmable FPGAs and SoCs to implement high-clock-rate signal processing functionality typically used by the datapath of digital radio applications.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

How to Waive DRC Results Using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

chalk talks

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

latest papers and content

Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

How to Automatically Replace LEF Abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

How to Waive DRC Results Using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Multi-Board Electrical and Thermal Co-Simulation Using PowerDC

Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.

TimingDesigner: Complex Diagrams

This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

How to easily setup Calibre in Virtuoso for multiple cell windows

This video shows how to setup Calibre Interactive to quickly select from multiple cells open in Virtuoso. Previously there was not a convenient way to setup Calibre Interactive when you wanted to run Calibre in different cells that are simultaneously open in the same Cadence session but now the Layout Cell Browser capability in Calibre Interactive provides an easy and convenient way to select from multiple cells open in Virtuoso.

How to Debug Double Patterning results using Calibre RealTime

This video shows how to easily debug Double Patterning results in Calibre RealTime by using the CTO file to assign different highlight colors to the warning and conflict ring results and to the mask1 and mask2 output layers.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

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PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

New Episode - Design Starts and Revisions - Designing With Altium Series

Find out more about Altium Designer, Altium’s development of Vault-Driven Electronics Design and Designing with Altium by watching this video series.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Xilinx and Agilent Verify DDR4 Controller and Interface Running at 2400 Mb/s

See a 2400 Mb/s DDR4 memory interface design running on an UltraScale™ FPGA demonstrate great signal quality and JEDEC compliance as verified by one of Agilent's newest test solutions, the Infinium 90000X-Series oscilloscope.

Guaranteeing Silicon Performance with FPGA Timing Models

Altera® timing models provide a simple and easy way to verify the timing of FPGA designs without the need to perform full physical electrical extractions and simulations. The three different operating corners available for 65-nm and newer FPGAs provide a thorough coverage of the time delays within the recommended operating conditions.

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

Troy Scott, Product Marketing Manager, and Peter Zhang, R&D Engineer, explain RTL debug features available in ProtoCompiler.

Troubleshooting and Fast Fault Isolation with VTOS

Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.

Advanced Timing Exception Multicycle Path Constraints

Learn Xilinx recommendations for constraining multicycle path constraints. Understand and apply multicycle path exception constraints in your design.

Implementing a Cost-Effective Human-Machine Interface for Home Appliances

Traditionally, HMIs for home appliances have been composed of mechanical devices such as buttons and knobs, coupled with display indicators such as LEDs and VFDs. Today there is a massive transformation occurring throughout the home appliance and consumer device markets. As the cost of LCDs drops due to the proliferation of the technology in consumer devices, LCDs with highly interactive GUIs are being deployed as a cost-effective replacement for the HMIs currently found on most home appliances.

IGLOO FPGA Product Brochure

Microsemi’s IGLOO®2 FPGAs offer best-in-class feature integration coupled with the lowest power, highest reliability and most advanced security in the industry. The device’s high level of integration provides the lowest total system cost versus competitive FPGAs while improving reliability, significantly reducing power and providing unparalleled security.

Increased Productivity Using Team Design

Xilinx® FPGAs offer up to 2 million logic cells in capacity—and they continue to grow. Designs of this complexity usually require a team of developers, and often, a team leader, who is responsible for the synthesis and implementation of the entire design. To make matters more challenging, the developers can be located internationally, with different portions of the design developed in different locations, and even by different companies. The Xilinx Team Design flow introduced in ISE® Design Suite 13.1 focuses on solving these challenges.

HDR-60 Overview

Watch the 5-minute HDR-60 Overview Video to: Understand the features and capabilities of the HDR-60 development kit, See the exceptional performance of the HDR-60 Video Camera Development Kit, Performing Fast Auto Exposure that quickly adjusts to changing light, Delivering greater than 120dB High Dynamic Range (HDR) Performing high quality Auto White Balance

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Understanding Single Event Effects (SEEs) in FPGAs

With the increasing popularity of programmable logic, FPGAs are finding their way into many applications that were once the territory of ASICs and ASSPs. At the same time, process nodes are shrinking and logic density is increasing, meaning that more of the system can be implemented in a single device. As programmable logic finds its way into avionics, communications and medical applications, designers face demands for increased reliability and safety over many of the traditional markets for FPGAs.

Implementing High-Performance FIR Filters and FFTs in 28nm FPGAs

Finite impulse response (FIR) and fast Fourier transforms (FFTs) are two of the most common digital signal processing (DSP) functions implemented in FPGAs. In this webcast, you’ll learn how the FPGA industry’s first variable-precision DSP architecture, available in 28nm Altera® FPGAs, is optimized for FIR and FFT implementation.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Allegro 16.5 Powers up Allegro PCB PDN Analysis

This is a Cadence blog post about the launch of the Allegro PDN Analysis and what it will mean for PCB designers.

Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays video, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses specs for USB 2.0 and USB 3.X in detail.


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