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Improve Reliability with Accurate Voltage-Aware DRC

Consumer expectations for longer device operations at sustained performance levels means designing for reliability is no longer an optional product feature, but a necessary and integral part of a product’s specifications. Power challenges in today's integrated circuit (IC) designs create a significant increase in verification complexity. Read more of this whitepaper to learn how to go beyond the traditional triumvirate of DRC, LVS, and ERC to provide robust reliability verification throughout the design flow and ensure maximum design efficiency.

SystemVision® Multi-discipline System Verification Datasheet

The SystemVision multi-discipline collaboration environment lets you explore concepts, validate performance specifications, investigate architectural partitions, and integrate implementation-level details, all in an easy-to-use virtual prototyping environment. Focus on a single design domain, or combine multiple domains, for full-system verification.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

A Significant Technology Advancement in High-Speed Link Modeling and Simulation

This white paper describes how Altera's jitter/noise eye (JNEye) link analysis tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the requirements for accuracy and advanced simulation and modeling techniques.

Allegro 16.5 Powers up Allegro PCB PDN Analysis

This is a Cadence blog post about the launch of the Allegro PDN Analysis and what it will mean for PCB designers.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Reduce Verification Complexity in Low/Multi-Power Designs

The increasing demand for highly reliable products covers many industries, all process nodes, and almost all design implementations. To satisfy this demand, reliability requirements are growing in all market segments.Accurate and repeatable reliability verification is now a critical capability, both for advanced nodes and for increasingly complex products being produced at established nodes. Read more of this whitepaper to learn how to create an easy-to-use, automated verification solution for low-power and multi-power domain designs.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Quick SI Simulation in OrCAD PCB Editor

Starting in 16.5 and continuing to the present version (16.6), you can perform signal integrity (SI) analysis from your OrCAD PCB board file while using only your OrCAD PCB Professional license (no special SI licenses needed!) This blog post will take a step by step approach and show you just how that is possible.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

400G Ethernet in Virtex UltraScale with 4x Sumitomo Electric CFP4 Optical Modules

Watch a demonstration of the industry’s first single chip solution for 400G applications, featuring the 20 nm Virtex® UltraScale™ device interfacing to Sumitomo Electric CFP4 optical modules and 10 km of optical fiber.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

UltraScale Devices Integrated 100G Ethernet IP Demo

See a demonstration of the integrated 100G Ethernet MAC and CAUI-4 IP available on UltraScale™ devices. This IP offers savings of up to 80K LUTs and 90% power over a soft implementation and simplifies your design process and time to market by providing proven functionality.

chalk talks

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Timing Closure in FPGA Designs Made Easy with PlanAhead

In this episode of Chalk TalkHD Amelia chats with Frederic Rivoallon of Xilinx and they attempt to unravel the mysteries of timing closure and reveal that yes, you can get timing closure right the first time in your next design.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

latest papers and content

Reduce Verification Complexity in Low/Multi-Power Designs

The increasing demand for highly reliable products covers many industries, all process nodes, and almost all design implementations. To satisfy this demand, reliability requirements are growing in all market segments.Accurate and repeatable reliability verification is now a critical capability, both for advanced nodes and for increasingly complex products being produced at established nodes. Read more of this whitepaper to learn how to create an easy-to-use, automated verification solution for low-power and multi-power domain designs.

Improve Reliability with Accurate Voltage-Aware DRC

Consumer expectations for longer device operations at sustained performance levels means designing for reliability is no longer an optional product feature, but a necessary and integral part of a product’s specifications. Power challenges in today's integrated circuit (IC) designs create a significant increase in verification complexity. Read more of this whitepaper to learn how to go beyond the traditional triumvirate of DRC, LVS, and ERC to provide robust reliability verification throughout the design flow and ensure maximum design efficiency.

400G Ethernet in Virtex UltraScale with 4x Sumitomo Electric CFP4 Optical Modules

Watch a demonstration of the industry’s first single chip solution for 400G applications, featuring the 20 nm Virtex® UltraScale™ device interfacing to Sumitomo Electric CFP4 optical modules and 10 km of optical fiber.

SystemVision® Versatile System Modeling Datasheet

SystemVision models circuits to systems in a single, easy-to-use analysis environment. Build systems and circuits using models from SystemVision’s large VHDL-AMS and SPICE model libraries. Model component tolerance, distribution, and stress details to improve system performance and reliability. Build and share libraries of custom simulation models.

SystemVision® Multi-discipline System Verification Datasheet

The SystemVision multi-discipline collaboration environment lets you explore concepts, validate performance specifications, investigate architectural partitions, and integrate implementation-level details, all in an easy-to-use virtual prototyping environment. Focus on a single design domain, or combine multiple domains, for full-system verification.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with John Stabenow of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Allegro 16.5 Powers up Allegro PCB PDN Analysis

This is a Cadence blog post about the launch of the Allegro PDN Analysis and what it will mean for PCB designers.

Quick SI Simulation in OrCAD PCB Editor

Starting in 16.5 and continuing to the present version (16.6), you can perform signal integrity (SI) analysis from your OrCAD PCB board file while using only your OrCAD PCB Professional license (no special SI licenses needed!) This blog post will take a step by step approach and show you just how that is possible.

Select the Right Performance for a 802.11ac/Advanced LTE AFE

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind choosing the right ADC in and Analog Front End for wireless (802.11ac and/or 3G/3G) communication systems. Learn more about Cadence IP at http://ip.cadence.com.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

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Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components

Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA). This paper describes the challenges confronting the designer and proposes a new tool leveraging ARM and Cadence technology to overcome the challenges of today’s highly integrated, multi-processor system-on-chip (SoC) designs.

Xilinx UltraScale: The Next-Generation Architecture for Your Next-Generation Architecture

UltraScale ™ architecture-based FPGAs extend Xilinx’s highly successful Virtex® and Kintex® FPGA and 3D IC families and enable massive data flow, system performance and lower power. To learn how the UltraScale architecture addresses key design challenges by applying leading-edge ASIC techniques in a fully programmable architecture, read the whitepaper.

System Design with Advance FPGA Timing Models

Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.

Reliable Reset Generation for TI DSP Processors

Every requires a reset generator circuit or IC to start up from a fixed condition after the supplies are turned on, and prevent the processor from executing instructions incorrectly and causing flash memory corruption. Traditional, simple, single-supply reset generators were adequate for single supply processors, but no longer are sufficient to guarantee reliable operation of multiple supply processors. This white paper examines some of the challenges associated with resetting modern processors.

Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays video, Moshik Rubin discusses the history of the PCI Express standard. Moshik starts with PCIe Gen1, which originated in 2002, and walks through the doubling of throughput offered by each new generation, ending with PCIe Gen4.

Lower Power and Boost System Bandwidth on 28nm FPGAs

It’s a challenging balancing act to meet growing bandwidth demands without increasing cost or power consumption. And it’s probably a challenge you know well if you’re designing high-end systems in areas such as communications, broadcast, military, and computer/storage. Achieve the right balance with Altera’s Stratix® V FPGAs, which deliver breakthrough bandwidth, reduced cost, and the lowest total power.

Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!

4 Reasons Why FPGAs are Right for Motor Control

Did you know that you can build a flexible and scalable motor control system in a single FPGA? Watch this 6-minute video to: Learn about the 4 reasons why FPGAs are right for motor control? How implementing a simple feedback mechanism can synchronize two motors, Leverage versatile design tools such as our Qsys integration tool for a scalable motor control solution, See two demonstrations of the BeMicro SDK-based Motor Control Kit (BeInMotion).

Understanding Metastability in FPGAs

Metastability is a phenomenon that can cause system failure in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This paper describes metastability in FPGAs, explains why the phenomenon occurs, and discusses how it causes design failures. The MTBF due to metastability indicates whether steps should be taken to reduce the chance of such failures. This paper explains how MTBF is calculated, and how both vendors and designers can increase it.

IP Integrator Advanced User Tips

Learn about Vivado® IP Integrator advanced user tips including: options for automatically zooming and making selections, searching for objects in a diagram, creating hierarchy, adding comments to a diagram, using layers and changing default colors on interfaces.

The Breakthrough Advantage for FPGAs with Tri-Gate Technology

This white paper examines the impact of transistor design transitions in the semiconductor manufacturing industry from traditional planar to 3-D structures, and how it will provide a significant boost in high-performance programmable logic speed, power, and production availability. This paper also provides a background on the development and state of Tri-Gate technology and accesses the benefits of Tri-Gate technology through Altera® FPGAs.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

“Smart” Connected Home Entertainment with Android

Experience the SmartCE (Connected Entertainment) for Android platform from MIPS Technologies in this new video demonstration. The SmartCE Platform enables MIPS licensees and their customers to bring differentiated connected entertainment solutions to market quickly.

The Importance of IP at STMicroelectronics

Peter Hirt, IP Procurement & IP Partnership Manager at STMicroelectronics, details the role of IP in advanced node designs, IP provider requirements and Cadence's comprehensive IP portfolio.

Virtex-7 2000T FPGA for ASIC Prototyping & Emulation

Watch this video to learn how a complex SoC platform was mapped into a single Virtex®-7 2000T FPGA, the world's largest 3D IC in volume production. With well over 2 million logic cells, the Virtex-7 2000T reduces the need for design partitioning and simplifies the mapping of ASIC RTL. This breakthrough capacity coupled with Xilinx's Next Generation Vivado™ Design Suite provides the ideal solution to tackle the demands of leading edge ASIC and SoC devices.

Unlock New Levels of Productivity for Your Design Using ISE Design Suite 12

In addition to the anticipated performance improvements commensurate with the production release of a Xilinx tool suite, the release of ISE v12 software unveils significant innovations with far-reaching potential. A new power-optimization capability called intelligent clock gating can reduce dynamic power by up to 30%. An innovation called design preservation vastly improves the user’s ability to achieve and maintain timing closure and design repeatability.

Easily Create PCIe-Based Designs for FPGAs

When implementing high-bandwidth PCI Express® (PCIe®) designs on FPGAs, success is never guaranteed. You want to spend your time creating custom logic that differentiates your design in the marketplace, not doing tedious work like manually wiring up all the components. Get your design to market faster and with less effort by using tools that free you up to complete the creative design work. These innovations will help you avoid the complexities of PCIe implementation, such as Transaction Layer Packet encoding and decoding, along with the mundane tasks of system integration like width matching, clock domain conversion, and arbitration. This way, you can dramatically shorten your FPGA design and verification cycles, meet performance requirements, and increase your overall design productivity.


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