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Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

SDSoc Development Environment Backgrounder

This backgrounder describes the features and benefits of the SDSoC™ Development Environment. The SDSoC development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use an Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Introducing the SDSoC Development Environment

The SDSoC™ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Cognitive Layering Technique for Low-Energy, Sensor-Rich Devices

In this week's Whiteboard Wednesdays video, Chris Rowan talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Major Enhancements of the PCIe Gen 4 Specification

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the latest enhancements of PCI Express (PCIe) Gen 4 and how these enhancements address the goals of increased bandwidth while maintaining software compatibility and keeping power consumption and implementation costs down.

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

chalk talks

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

latest papers and content

Cognitive Layering Technique for Low-Energy, Sensor-Rich Devices

In this week's Whiteboard Wednesdays video, Chris Rowan talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

Using the ARM AMBA Protocol

In this week's Whiteboard Wednesdays video, Avi Behar follows up on his earlier video on the ARM® AMBA® protocol family. Watch this video for a deep dive on each of the protocols in the ARM AMBA family to learn how they are commonly used.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

Shaving Weeks Off PCB Design Cycle Via Auto-Routing

To keep up with product refresh cycles as well as quality expectations, the Polycom hardware team decided it was time to move to auto-routing of their PCB boards, using tools including OrCAD Capture CIS for schematic design entry and synchronization/validation of parts data, Allegro PCB Designer for constraint-driven design, and Allegro PCB Router for auto-routing.

SDSoc Development Environment Backgrounder

This backgrounder describes the features and benefits of the SDSoC™ Development Environment. The SDSoC development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use an Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

Introducing the SDSoC Development Environment

The SDSoC™ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment.

Major Enhancements of the PCIe Gen 4 Specification

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the latest enhancements of PCI Express (PCIe) Gen 4 and how these enhancements address the goals of increased bandwidth while maintaining software compatibility and keeping power consumption and implementation costs down.

How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse

Engineering teams are under more pressure than ever before as SoCs grow more complex and design schedules become increasingly tighter. With its productivity advantages, high-level synthesis (HLS) has long been touted as part of the solution, but its sweet spot has traditionally been limited to datapath-centric blocks. Moreover, design productivity is only one part of the equation. Verification is often an even bigger hurdle. This paper discusses how HLS can be used to improve the design, verification, and reuse of intellectual property (IP). The paper also introduces a new HLS tool that provides excellent power, performance, and area (PPA) results across the digital design space.

Blu Wireless Boosts SystemC Design and Verification Productivity Using High-Level Synthesis Technology

As SoCs continue to grow in size and complexity, the SystemC design language has emerged as an effective means of design verification. High-level synthesis (HLS), in turn, is proving to be an ideal methodology to increase SystemC design and verification productivity. This paper presents a case study of how Blu Wireless Technology ramped up quickly with a working prototype of its WiGig millimeter wave baseband technology via a streamlined design and verification process based on SystemC and HLS.

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Firm Error Immunity in Flash FPGAs

Radiation effects are not isolated to space electronics only, but they affect all type of electronics whether they are automotive, industrial or military and avionics. What differentiates them is the type of radiation. This webcast shows how FPGA’s interact with them and why Actel FPGAs are the best solution to mitigate these effects.

Tips for Creating Effective Hybrid Virtual Prototypes

Creating a virtual prototype becomes more challenging when graphics cores are involved because they have different instruction sets than CPUs. Watch this video to hear Robert Kaye, technical specialist with the Development Solutions Group at ARM, share tips and techniques for creating hybrid virtual platforms with the Cadence® Palladium® XP platform and accelerated verification IP.

Xilinx UltraScale: The Next-Generation Architecture for Your Next-Generation Architecture

UltraScale ™ architecture-based FPGAs extend Xilinx’s highly successful Virtex® and Kintex® FPGA and 3D IC families and enable massive data flow, system performance and lower power. To learn how the UltraScale architecture addresses key design challenges by applying leading-edge ASIC techniques in a fully programmable architecture, read the whitepaper.

Xilinx FPGAs in Portable Ultrasound Systems

There has long been a need for portable ultrasound systems that have good resolution at affordable cost points. Portable systems enable health care providers to use ultrasound in remote locations such as disaster zones, developing regions, and battlefields, where it was not previously practical to do so.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

First Xilinx Virtex-7 FPGA Demonstration

Watch demonstration of the second device in the Xilinx 28nm FPGA family -- the high performance Virtex-7 XV485T.

Reduce Verification Complexity in Low/Multi-Power Designs

The increasing demand for highly reliable products covers many industries, all process nodes, and almost all design implementations. To satisfy this demand, reliability requirements are growing in all market segments.Accurate and repeatable reliability verification is now a critical capability, both for advanced nodes and for increasingly complex products being produced at established nodes. Read more of this whitepaper to learn how to create an easy-to-use, automated verification solution for low-power and multi-power domain designs.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Advanced Timing Exception Multicycle Path Constraints

Learn Xilinx recommendations for constraining multicycle path constraints. Understand and apply multicycle path exception constraints in your design.

High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design

The rapid change in today's design environment requires a programmable solution that provides the highest performance and lowest power at the lowest cost. To meet the needs of high-volume systems, it is essential that the solution uses the latest 45 nm high-volume technology.

Xilinx at NAB 2014 | OmniTek OZ 745

Michael Hodson, President of OmniTek, demonstrates their Scalable Video Pipeline and the Real-time Video Engine OZ 745 development platform which is based on the Zynq® 7045 AP SoC.

Virtex-7 2000T FPGA for ASIC Prototyping & Emulation

Watch this video to learn how a complex SoC platform was mapped into a single Virtex®-7 2000T FPGA, the world's largest 3D IC in volume production. With well over 2 million logic cells, the Virtex-7 2000T reduces the need for design partitioning and simplifies the mapping of ASIC RTL. This breakthrough capacity coupled with Xilinx's Next Generation Vivado™ Design Suite provides the ideal solution to tackle the demands of leading edge ASIC and SoC devices.

The Power Management IC for the Intel® AtomTM Processor E6xx Series and Intel® Platform Controller Hub EG20T

Time to market, cost, board size constraints, reliability and design capabilities are among the motivating factors in choosing Power Management IC versus a discrete solution. However, a discrete solution allows design optimization, offers higher power efficiency, flexibility and is easy to debug. Often, it is not possible to determine which choice will be better without understanding the details of design requirement. This paper aims to discuss both the advantages and disadvantages of using Power Management IC versus a discrete solution on the Intel® AtomTM Processor E6xx series platform.

Accelerate Design Productivity with Vivado Design Suite 2013.2

The Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. For More Vivado Tutorials please visit: www.xilinx.com/training/vivado

SystemVision® Multi-discipline System Verification Datasheet

The SystemVision multi-discipline collaboration environment lets you explore concepts, validate performance specifications, investigate architectural partitions, and integrate implementation-level details, all in an easy-to-use virtual prototyping environment. Focus on a single design domain, or combine multiple domains, for full-system verification.

Introduction to SmartFusion Intelligent Mixed Signal FPGAs

This short video gives an overview of the SmartFusion™ intelligent mixed signal FPGAs introduced, including the microcontroller subsystem (MSS), analog compute engine (ACE) and FPGA.

Accelerate LTE Basestation Design and Development

Significantly reduce system cost, power dissipation, and form factor in eNodeB design with the LTE Baseband Targeted Design Platformintegrated with Wintegra Winpath-3 networking and MAC to form a full eNodeB on a single width AMC card.


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