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Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

UltraScale Devices Integrated 100G Ethernet IP Demo

See a demonstration of the integrated 100G Ethernet MAC and CAUI-4 IP available on UltraScale™ devices. This IP offers savings of up to 80K LUTs and 90% power over a soft implementation and simplifies your design process and time to market by providing proven functionality.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Using Low Cost, Non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design. Learn more about Cadence IP at http://ip.cadence.com.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

chalk talks

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Hardware/Software Co-Verification of ARM Processor-Based Designs

In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti of EvE about the latest in emulation technology and explains how you can use emulation to dramatically accelerate software development, which is becoming the most time-consuming part of SoC design.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

latest papers and content

Select the Right Performance for a 802.11ac/Advanced LTE AFE

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind choosing the right ADC in and Analog Front End for wireless (802.11ac and/or 3G/3G) communication systems. Learn more about Cadence IP at http://ip.cadence.com.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Aldec Active HDL Datasheet

Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager. Active-HDL has interfaces to over 80 leading EDA tools, making it the most powerful environment. Check out the top features and product configurations to see if Active-HDL is right for you.

Formal VIP for 100% Accurate Designs

In this week's Whiteboard Wednesdays video, Tom Hackett discusses formal verification IP (VIP), how it supports formal analysis, and how design engineers can leverage formal VIP to ensure their designs are 100% correct. Learn more about Cadence IP at http://ip.cadence.com.

How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design. Learn more about Cadence IP at http://ip.cadence.com.

Reduce Project Schedules and Increase Quality using Model Driven Development for Design, Verification, and Test

This paper shows how Model Driven Development can address common challenges in the system design, verification & testing of complex systems. Project success requires that hardware, software, and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components, which often proves to be costly in terms of time, money, and engineering resources. This paper covers such solutions that reduce project schedule while improving product release quality.

Modernizing System Development

Allowing disconnected development and waiting until the latest program stages to perform systems integration and connect all the pieces is a high risk situation, yet one all too common in today’s product realization process. Bringing domain expertise together as appropriate throughout a project’s development process is imperative for project success.  This paper explores a more modern approach to system development built on a Model Driven Development (MDD) approach.

Successfully Designing FPGA-Based Systems

One key challenge in successfully designing FPGA-based systems is choosing the right FPGA for the design needs, and maximizing the use of FPGA resources. In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.

Addressing the “Power-Aware” Challenges of Memory Interface Designs

One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing high-speed memory interfaces. This paper assesses how modern tools can be used to address power-aware SI challenges with I/O modeling, interconnect modeling, simulation, and analysis.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis Tech Packet

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Vivado Advanced Exceptions Clock Group Constraints

Learn Xilinx recommendations for constraining clock group exceptions; specifically in detail what these constraints are and also see a few examples. Understand and apply the clock group exception constraints in your design.

Market-Specific Custom IC Solutions

When it comes to custom IC design, one size most definitely does not fit all. Different applications call for specialized IP, tools, and even semiconductor processes. But, sorting through the options can be a daunting process. In this episode of Chalk Talk, Amelia Dalton chats with Pavel Klinger from GLOBALFOUNDRIES about market-specific solutions that can get your product to market faster and with lower risk than ever.

Introducing Xilinx Ultrascale™ Architecture: Industry’s First ASIC-Class All Programmable Architecture

The UltraScale™ Architecture addresses these challenges by applying leading-edge ASIC techniques in a fully programmable architecture. This architecture scales from 20nm planar through 16nm FinFET technologies and beyond, while also scaling from monolithic through 3D ICs. The UltraScale architecture not only addresses the limitations to scalability of total system throughput and latency, but directly addresses interconnect - the number one bottleneck to system performance at advanced nodes.

SmartFusion2 System-on-Chip FPGAs Product Brief

Microsemi’s SmartFusion®2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex™-M3 processor, and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. SmartFusion2 offers up to 3.6X the gate density and up to 2X the performance of previous flash-based FPGA families and includes multiple memory blocks and multiply accumulate blocks for DSP processing. The 166 MHz ARM Cortex-M3 processor is enhanced with an embedded trace macrocell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals, including controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include PCI EXPRESS® (PCIe®), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) plus native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high speed memory interfaces.

Internet of Things (IoT) Design Considerations for Embedded Connected Devices

Embedded connectivity has been around since the early days of M2M. But what is new are the many complexities and emerging standards embedded system developers need to know if they are to design the latest IoT device. This paper delves into many of the key considerations developers need to know and discusses the critical areas of IoT security and connectivity along with the importance of a proven RTOS.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Video Sneak Peek: Industry’s First 28-Gbps FPGA

If you are seeking a device that is fast, reliable, and gives you high bandwidth, seek no further. Our 28-nm Stratix® V FPGAs are just what you need for your high-end designs such as 100G applications. Watch this 5-minute video to get an initial look at our high-performance Stratix V FPGA running at 28 Gbps. You will: See the transmit eye at 28 Gbps running a PRBS-31 test pattern, See the receiver performance at 28 Gbps, and learn about the transceiver architecture that provides high performance, power efficiency, and reliability.

Conquer FPGA Design Complexity with System-Level Integration

Having trouble meeting deadlines? Is your FPGA design growing but when you look around, your team is still the same size, or worse, smaller? Do you wish reusing someone else’s design would work seamlessly? Watch this webcast to see how you can increase your FPGA design productivity. Find out how to quickly develop large, complex systems by integrating other smaller complete systems and intellectual property (IP).

Meeting the Performance and Power Imperative of the Zettabyte Era with Generation

Today’s Information and Communications Technology (ICT) equipment developers face a daunting problem in addressing exponential growth in bandwidth demand while minimizing power consumption. This white paper outlines the performance and power requirements for next-generation programmable logic solutions to meet the demands of the growing ICT sector by leveraging multiple process technologies and revolutionary approaches to transistor design, new architectures, and comprehensive device-level power features.

Accelerate Your Video Processing Application Using Reference Designs

Wouldn´t you like an integrated solution that makes developing broadcast infrastructure equipment easier and faster? Watch this new 9-minute video to learn about two development kits and reference designs that do just this.

Implementing Next-Generation Passive Optical Network Designs with FPGAs (REVISED)

FPGAs play a key role for early adopters of next-generation passive optical network (PON) systems due to their flexibility to allow development of future proof designs and implementation of unique features to differentiate against competitors versus standard products. Altera® Stratix® V FPGAs’ abundant resources, robust transceivers with native PON burst mode support, and fast external memory interfaces bring an unprecedented level of system integration. Altera further helps to lower system cost and power consumption via its seamless migration path from FPGAs to its HardCopy® series ASICs.

Implementing PCI Express Bridging Solutions in an FPGA

As system bandwidths increase, more applications are moving to SERDES-based interfaces like PCI Express. Newer generation FPGAs with embedded SERDES, like the LatticeECP3 devices, can be used to support a variety of serial protocols like PCI Express, providing a single FPGA platform for multiple designs.

Addressing 100-GbE Line-Card Design Challenges on 28nm FPGAs (REVISED)

As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G production systems. Because of this, service providers are looking at emerging 40-GbE/100-GbE standards for their next-generation line card options. Altera’s Stratix V FPGAs solve the bandwidth problem by providing integrated 12.5-Gbps transceivers with hardened 100G PCS functions on the 28-nm technology node.

Strategies to Develop Secure and Robust Embedded Devices

Learn a pragmatic approach to configuring a heterogeneous multicore ARM® device built with ARM TrustZone™ technology and trade-offs of various implementations.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis Tech Packet

Debugging Machine Check Exceptions on Embedded IA Platforms

Embedded systems must be able to detect, recover from and report errors. This is a critical feature during debugging and also for quality control after product manufacturing has commenced. Advanced error handling is especially important for embedded systems. This white paper presents a step-by-step approach to debugging machine check exceptions and understanding their causes are resolving errors in embedded Intel® architecture platforms.


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