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Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Hardware in the Loop from the MATLAB/Simulink Environment

This white paper describes the tools, design flow, and verification of systems using Altera(r) FPGAs. It discusses the techniques of software simulation and hardware testing, and the challenges associated with them. This paper also describes the advantages of using the Hardware in the Loop (HIL) tool, which is part of Altera's software tools, to simplify software simulation and hardware testing in a variety of applications.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

System Design with Advance FPGA Timing Models

Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Defining Different Types of USB Controllers

In this week's Whiteboard Wednesday video, Jack Duda takes a closer look at different types of USB controllers and their roles in today's devices.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

Solving the ASIC Prototype Partition Problem with Synopsys ProtoCompiler

When developing a multi-FPGA prototype of an ASIC or SOC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules should be assigned to each FPGA; where and how many cables connect the FPGAs; and how to squeeze all the signals into those cables. All these decisions need to result in the fastest possible prototype that you can build and debug in the allotted time. And every week the RTL changes, and sometimes it seems that every decision you make forces you to revisit all the decisions that came before.There is a better way.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Get to Know 802.11a/c Wireless Analog Front End Solution

In this week's Whiteboard Wednesday video, Priyank Shukla discusses Cadence's wireless analog front end (AFE) solution for 802.11a/c.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

EWIS Requirements: The Business Challenge

Without proper planning and the evolution of their business to efficiently deal with the EWIS mandates, companies could find themselves in a very costly situation. This paper investigates the issues surrounding EWIS compliance and methods to minimize both cost and potential program delays.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

chalk talks

Spartan-6 FPGAs in Video Designs

In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

Super Low Power MCUs: NanoWatt XLP Technology

In this episode of Chalk TalkHD Amelia chats with Jason Tollefson of Microchip Technology about a radical new line of microcontrollers from Microchip that combine amazing processing capability with almost unbelievably low power consumption.

High Speed Data Acquisition and Software Defined Radio Made Simple

Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk TalkHD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Adding Wi-Fi to Your FPGA Design - Building a Connected Device

In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.

Digital Predistortion for Base Station Power Amplifiers

In this episode of our new Chalk TalkHD series, Amelia Dalton talks to Todd Nelson from Linear Technology about how digital predistortion (DPD) can be used to save millions of dollars worth of power in base station designs. DPD is simple to apply, and has a dramatic impact on the power amplifier - the most power-hungry part of modern base stations. In this Chalk TalkHD you'll hear how DPD works and how you can apply it to your next design.

latest papers and content

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Faster Wiring and Harness Design

Does your electrical design software just do the basics? Or does it take the complexities of today's designs out of the task and save you time and money? This short white paper outlines the top ten highlights of how new tools make wiring and harness design faster and better.

EWIS Requirements: The Business Challenge

Without proper planning and the evolution of their business to efficiently deal with the EWIS mandates, companies could find themselves in a very costly situation. This paper investigates the issues surrounding EWIS compliance and methods to minimize both cost and potential program delays.

EDS Design Tools for Electric Vehicles

This paper explores how challenges for electric vehicles from battery placement to electrical distribution to eliminating crosstalk between high- and low-level signals can be solved with advanced EDS software. Also see how design environments incorporate features for designer to address product plans and answer tomorrow's demand for fully electric vehicles.

Injecting Automation into Verification – Improved Throughput

This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Defining Different Types of USB Controllers

In this week's Whiteboard Wednesday video, Jack Duda takes a closer look at different types of USB controllers and their roles in today's devices.

Get to Know 802.11a/c Wireless Analog Front End Solution

In this week's Whiteboard Wednesday video, Priyank Shukla discusses Cadence's wireless analog front end (AFE) solution for 802.11a/c.

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SmartFusion2 SoC FPGA – Dynamic Configuration of AHB Bus Matrix

SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) devices support advanced high performance bus (AHB) bus as a multi-layer AHB matrix. SmartFusion2 SoC FPGA devices AHB bus matrix has ten masters and seven direct slaves. This application note describes how to configure the weight values dynamically for the AHB bus matrix masters to access the AHB bus matrix slave using the weighted round-robin (WRR) arbitration. This application note also provides a reference design with two fabric masters connected to the FIC_0 and FIC_1 interfaces. The two fabric masters can access a single slave eSRAM1 using the WRR arbitration.

Size, Reliability and Security The Essential Ingredients for Medical Devices

Improved electronics technology will bring a new generation of devices that provide portability, connectivity, lower cost and data security. With the trend towards miniaturization comes the requirement for improved security to maintain patient confidentiality. Reliability is also a requirement, both in terms of product longevity and assurance that the device is working as specified. This is crucial for the rapidly expanding market for devices used in emergency interventions. Microsemi's nonvolatile customizable system-on-chip (cSoC) devices and FPGAs provide the right combination of features to let equipment makers deliver on all those demands.

World's Smallest FPGAs Solve 4 Big Problems

In this episode of Chalk Talk, Amelia chats with Gordon Hands (Lattice Semiconductor) about some awesomely tiny FPGAs that bring the power of programmable logic into devices like cell phones, tablets, and other power and form factor sensitive applications.

High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design

The rapid change in today's design environment requires a programmable solution that provides the highest performance and lowest power at the lowest cost. To meet the needs of high-volume systems, it is essential that the solution uses the latest 45 nm high-volume technology.

Achieving 1066-MHz DDR3 Performance With Advanced Silicon and Memory IP

FPGA applications are demanding higher memory bandwidth and greater performance. To meet these requirements, we offer external memory solutions that are faster, better, and easier to use.

Scale Beyond 1080p with 4K Design Methodology

Looking for a cost-effective and efficient way to implement 4K and multi-channel video processing? As the world of video progresses to 4K and beyond, the need for higher performance and bandwidth makes system development more complex and expensive.

SmartFusion2 FPGAs: Breakthrough Capabilities for Advanced Security, High Reliability and Low Power FPGA Applications

Microsemi has created the new SmartFusion®2 family of system-on-chip (SoC) field programmable gate arrays (FPGAs), which directly address these challenges and deliver the advanced security, high reliability and low power capabilities that this growing class of mission critical applications demands. Additionally, Microsemi believes that these requirements are no longer relegated to a narrow class of applications, but span a majority of the deeply interconnected electronics systems being designed today. This white paper will illustrate how the Microsemi SmartFusion2 family holds the promise of creating a much more secure and reliable future for all of us.

Taking Advantage of Advances in FPGA Floating-Point IP

Recently available FPGA design tools and IP provide a substantial reduction in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover, unlike digital signal processors, an FPGA can support a DSP datapath with mixed floating- and fixed-point operations, and achieve performance in excess of 100 GFLOPS. This is an important advantage, for many high-performance DSP applications only require the dynamic-range floating-point arithmetic in a subset of the total signal processing.

Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors

Single event effects (SEEs) are of a growing concern in high-reliability system development, yet there is much disparity among users of ASICs and FPGAs with regard to understanding how susceptible their designs might be.

Freescale Utilizes the Cadence Low-Power and Mixed-Signal Solutions to Verify Kinetis Products

Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence® Low-Power and Mixed-Signal Solution to verify the company’s Kinetis Microcontroller products targeted for automotive and internet-of-things applications.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Solutions for Mixed-Signal IP, IC, and SoC Implementation

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Modern mixed-signal designs require new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implementation challenges and focuses on three advanced, highly integrated flows to meet those challenges.

Using FPGAs to Render Graphics and Drive LCD Interfaces

This paper describes the use of FPGAs to add a LCD and GUI display to any embedded system. Unlike fixed processor device implementations, this approach is scalable and supports any display interface. Graphics can be generated by any external processor, embedded processor, or hardware graphics acceleration engine integrated into the same FPGA design. The benefits of FPGA implementation and available tools and IP are described, and links to reference designs and solution providers are given.

Zynq-7000 All Programmable SoCs Deliver Unmatched Performance and Power

Xilinx Zynq®-7000 All Programmable SoC devices fuse a fast processor system (PS) based on two 1GHz ARM Cortex™-A9 MPCore processors with the industry’s fastest and most advanced 28nm programmable logic (PL) fabric, a large on-chip memory, multiple high-speed serial transceivers, numerous hardened peripheral IP cores including DDR and Flash memory controllers, and an on-chip analog-processing block that incorporates two 1Msamples/sec A/D converters. Zynq-7000 devices offer unmatched performance with low operating power.

Power Supply Transients on RTAX-S and RTSX-SU Devices

Single-event effects (SEE) during operation of power regulators can cause the output of the regulator to be as high as the regulator input for short durations, on order of tenths of microseconds. Consequently, any device that is powered by the regulator could see this supply glitch during normal operation of the device. This report summarizes the experiments and data collected to study the impact of these power supply glitches on the RTAX™-S and RTSX-SU devices on printed circuit boards.

Enabling New Applications with NFC Connectivity and Energy Harvesting

In this episode of Chalk TalkHD Amelia chats with Greg Proehl (STMicroelectronics) about the basics of NFC technology, and they explore some interesting NFC applications as well as cool and innovative new NFC solutions from ST - including one with energy harvesting capability.

CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS

In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC discusses an aggressive RF design with distortion problems in the lab, and how a solution was developed in collaboration with Cadence® FAEs using Cadence Spectre® Accelerated Parallel Simulator's distortion summary feature. This solution provided improved visibility into circuit operation to speed up the distortion-sensitive design cycle by 30%, and more deterministic silicon performance leading to fewer disconnects between simulation and lab. Learn more about the Spectre Accelerated Parallel Simulator at http://bit.ly/1tUYTQ1.

Imaging, Video, and Embedded Vision

In this week's Whiteboard Wednesdays episode, Gary Brown, from the Tensilica Imaging and Video Division at Cadence, talks about imaging, video, and embedded vision technologies that are being worked on today. Gary gives a high-level overview of the industry sectors and end products that leverage these technologies and some of the tradeoffs that need to be considered during the design process.


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