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4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Addressing the Advantages of Embedded LTE and Advanced LTE

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of embedding a LTE and Advanced LTE analog block on the SoC to support many of the mobile applications in the market today.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

UltraScale Architecture: Highest Device Utilization, Performance, and Scalability

The UltraScale™ architecture provides numerous technical innovations to exceed the utilization and performance demands of next-generation applications, all while offering both architectural migration and package footprint migration for optimal design reuse.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

A Complete Analog Design Flow for Verification Planning and Requirement Tracking

Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend common traits of CDV as used in digital verification to analog verification.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

The UltraScale Architecture for Highest Utilization and Superior Performance

The UltraScale™ architecture introduces many innovations over traditional FPGA architectures that increase performance and reduce power consumption. In this video, we will focus on enhancements to the routing, logic and implementation software that result in an architecture allowing for the device to be highly utilized while still maintaining performance, and keeping runtime low.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Announcing ProtoCompiler for Multi-FPGA Prototyping

Prototyping Automation and Debug Software for HAPS FPGA-Based Prototyping Systems Improves Prototyping Performance

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

chalk talks

Introducing SmartFusion2 FPGAs

In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about Microsemi's biggest FPGA announcement this year - SmartFusion2. This new family can do things we never expected from Microsemi's non-volatile FPGAs. Watch this Chalk Talk to learn what it's all about.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Power Supply Management in High-Availability Systems

One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Maximizing Battery Life with TI's Wolverine Technology

In this episode of Chalk TalkHD Amelia chats with Ryan Hoium (Texas Instruments) about about TI’s revolutionary Wolverine technology and a new series of ultra-low power MCUs that will change the way we think about batteries in our embedded designs.

Simplifying Industrial Ethernet Design

In this episode of Chalk TalkHD Amelia chats with Suhel Dhanani of Altera about the who, what, and how of industrial ethernet design.

latest papers and content

Three Ways that Allegro TimingVision Environment Speeds Up Timing Closure of High-Speed PCB Interfaces

On advanced high-speed interfaces, timing closure can be an iterative process that can be time-consuming and frustrating. PCB designers need techniques and tools to make the process more efficient, so they can contribute to an overall faster time to market for the design. This article discusses three ways that the new Cadence Allegro TimingVision Environment speeds up timing closure of high-speed PCB interfaces.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Addressing the Advantages of Embedded LTE and Advanced LTE

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of embedding a LTE and Advanced LTE analog block on the SoC to support many of the mobile applications in the market today.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design

Wireless RFIC designers are expected to be experts on a variety of ever-changing wireless standards and protocols. They must also contend with time-consuming manual simulation setup and post-processing of the simulation results. This paper discusses how an advanced simulation methodology, involving characterization and modeling of a RFIC design, enhances both the speed and the accuracy of system-level performance verification of a wireless RFIC.

UltraScale Architecture: Highest Device Utilization, Performance, and Scalability

The UltraScale™ architecture provides numerous technical innovations to exceed the utilization and performance demands of next-generation applications, all while offering both architectural migration and package footprint migration for optimal design reuse.

The UltraScale Architecture for Highest Utilization and Superior Performance

The UltraScale™ architecture introduces many innovations over traditional FPGA architectures that increase performance and reduce power consumption. In this video, we will focus on enhancements to the routing, logic and implementation software that result in an architecture allowing for the device to be highly utilized while still maintaining performance, and keeping runtime low.

OrCAD Constraint Driven Design Flow

The OrCAD constraint driven flow provides a unique, fully integrated environment to define design intent and dynamically track compliance throughout the entire implementation process. This slideshow is demonstrating how to utilize the constraint driven flow in OrCAD to improve efficiency, reduce errors, and help ensure on-time product delivery.

Design Data Management with PTC Windchill and Cadence Allegro PCB

Learn how PTC and Cadence have developed a unique collaboration environment to connect Allegro PCB design data with the Windchill PLM system for robust file management and check-in check-out capabilities.

Consumer DRAM Trends

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends in today's consumer market. He deep dives into the comparison between LPDDR4 and DDR4 DRAM.

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Power Estimation and Management for MachXO2 Devices

A key requirement for many of today’s high volume FPGA applications is low power consumption. The MachXO2™ PLD provides many power-saving features including Power Controller, Bank Controller and Power Guard. This technical note provides users with detail for using the MachXO2 low power architectural features including power supply considerations and power estimations provided by the Power Calculator tool.

Lower Power and Boost System Bandwidth on 28nm FPGAs

It’s a challenging balancing act to meet growing bandwidth demands without increasing cost or power consumption. And it’s probably a challenge you know well if you’re designing high-end systems in areas such as communications, broadcast, military, and computer/storage. Achieve the right balance with Altera’s Stratix® V FPGAs, which deliver breakthrough bandwidth, reduced cost, and the lowest total power.

Beyond Physical: Solving High-end FPGA Design Challenges

The advantages of using programmable logic to get electronic products to market quickly with less risk and cost are well known and recent market drivers have shifted even further in their favor; new economic realities coupled with changing consumer behavior, shorter product life cycles, richer feature sets, and faster upgrades, to name a few. In step with these demands, high-end FPGAs are now architected using geometries down to 40nm and with capacities of up to five million equivalent ASIC gates. They include performance optimized I/O’s and dedicated DSP architectures that together enable extremely powerful and cost-effective solutions. For these reasons, FPGAs are also widely used to realistically prototype and validate ASIC designs at orders of magnitude higher speeds than are possible with traditional acceleration or emulation based solutions.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

Xilinx UltraScale Architecture for High-Performance, Smarter Systems

The UltraScale™ architecture combines a successful architectural platform with numerous innovations and second-generation 3D IC technology to deliver breakthrough system performance, unprecedented capacity, and lower power. Based on the industry's first ASIC-class programmable architecture, Kintex® UltraScale and Virtex® UltraScale devices are enabling system OEMs to build smarter systems with fewer devices…faster. Read this white paper to learn more.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

How to Automatically Replace LEF Abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

TimingDesigner: Complex Diagrams

This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.

Versatile Digital QAM Modulator

Combined with enhanced DSP blocks, the logic structure of Altera’s Stratix® series and Arria® series FPGAs offer a flexible way to implement the key elements of the Quadrature Amplitude Modulation (QAM) signal-processing path in any region. With their innovative logic structure, enhanced dedicated DSP blocks, and the revolutionary memory blocks, Stratix series and Arria series FPGAs are perfect for cable head-end system designers who want flexibility and speedy time to market. In addition to these advanced features, Altera also provides an extensive set of IP cores and EDA tools to help simplify the design process.

MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 LUTs. In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM, Distributed RAM, User Flash Memory, PLLs, pre-engineered source synchronous I/O support and hardened versions of functions such as SPI controller, I2C controller and timer/counter. These devices are ideal for low cost, high volume consumer and system applications.

A Generation Ahead for Smarter Systems: 9 Reasons why the Xilinx Zynq-7000 All Programmable SoC Platform is the Smartest Solution

The Xilinx Zynq™-7000 All Programmable SoC is the ideal platform to infuse intelligence into today’s embedded systems. It is All Programmable, meaning that not only can one add systems intelligence through software, but additional data processing and decisions can be executed in real time with programmable hardware and system interfaces can be optimized and evolved through programmable I/O.

SmartFusion Intelligent Mixed Signal FPGAs in Motor Control Applications

This video provides an exploration of Motor Control applications using Actel's SmartFusion™ intelligent mixed signal flash FPGAs for field-oriented closed-loop motor control for brushless DC (PMSM) motors, with a closer look at your challenges and a look into the Actel motor control development kit currently in development.

Reducing Power Consumption and Increasing Bandwidth on 28nm FPGAs (REVISED)

Lower power consumption and higher bandwidth are the dominant requirements in designing next-generation high-end applications. The trend is for higher bandwidth in the same footprint at the same or lower power and cost as the Internet goes mobile. The march to 40G and 100G systems is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and cooling solutions often dominate the power budget, sometimes up to twice the power consumption of the electronics. Altera’s 28-nm FPGAs address these challenges through leading-edge technological innovation, integration, and reduced power consumption.

Why Do I Need a Customizable ARM-based SoC?

In this episode of Chalk TalkHD Amelia chats with Todd Koelling of Altera about what’s inside these new SoC FPGAs and how you can get started designing with them.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!


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