Search On Demand

 
 
 
 

Recommended Reading

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Industry’s 1st Single Chip 400GE Solution

Watch a demonstration of the industry’s first single chip solution for 400G applications, featuring the 20 nm Virtex® UltraScale™ device interfacing to Sumitomo Electric CFP4 optical modules and 10 km of optical fiber.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

chalk talks

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.

Maximize Design Productivity With PCIe/104 FPGA/Processor

In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Getting Started Using Kintex-7 FPGAs for DSP

In this episode of Chalk TalkHD Amelia chats with Tom Hill of Xilinx about their new Kintex-7 DSP development kits that will finally get you onto the rocket-coaster of FPGA-powered DSP.

latest papers and content

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Multi-Board Electrical and Thermal Co-Simulation Using PowerDC

Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.

TimingDesigner: Complex Diagrams

This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

How to easily setup Calibre in Virtuoso for multiple cell windows

This video shows how to setup Calibre Interactive to quickly select from multiple cells open in Virtuoso. Previously there was not a convenient way to setup Calibre Interactive when you wanted to run Calibre in different cells that are simultaneously open in the same Cadence session but now the Layout Cell Browser capability in Calibre Interactive provides an easy and convenient way to select from multiple cells open in Virtuoso.

How to Debug Double Patterning results using Calibre RealTime

This video shows how to easily debug Double Patterning results in Calibre RealTime by using the CTO file to assign different highlight colors to the warning and conflict ring results and to the mask1 and mask2 output layers.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

TimingDesigner Simple Diagrams

This video focuses on drawing simple diagrams in the TimingDesigner program. The presentation covers drawing clocks, signals and buses. It then moves on to edge events, which include delays and constraints. Lastly it covers edge events and the Parameter spreadsheet where it looks at variables, functions, and shows an example of a diagram of a Sharc DSP processor.

Introduction to TimingDesigner

TimingDesigner is the interactive timing analysis tool designers trust to deliver fast and accurate results for timing critical designs such as high-speed, multi-frequency designs. This video on TimingDesigner is a short introduction of the program. It will illustrate the interactive timing analysis and GUI interface, followed by a short demonstration that will highlight the parameter spreadsheet, library spreadsheet, and manager window in TimingDesigner.

How to select specific rule checks for a Calibre DRC run

This video shows you how to create specific rule check recipes for running DRC in Calibre Interactive. Rule check recipes allow you to configure and reuse specific rule checks such as metal, density, and antenna checks across multiple Calibre DRC jobs. This will reduce the runtime for your Calibre DRC jobs and allows you to focus on the Calibre DRC results that you want to fix.

Pattern Matching:  Blueprints for Further Success

Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process.

Lowering the Total Cost of Ownership in Industrial Applications

This white paper uses a design example to demonstrate that FPGAs are not only a more flexible option than discrete MCU, DSP and ASSP products, but also provide a lower total cost of ownership (TCO) as measured by development, enhancement, replacement, and maintenance costs over the lifetime of a system.

« Previous123456...59Next »

New To On Demand?

Registered users can access hundreds of whitepapers, demos, videos, webcasts and more. Sign up now.

Already a registered user? Log in here to access content.

subscribe to journal on demand weekly newsletter

more on demand

Broadcom Uses Palladium XP to Validate New Architecture of Mobile SoC

Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence(r) Palladium(r) XP to validate a new architecture for a complex mobile SoC for mobile platform devices.

Improve Reliability with Accurate Voltage-Aware DRC

Consumer expectations for longer device operations at sustained performance levels means designing for reliability is no longer an optional product feature, but a necessary and integral part of a product’s specifications. Power challenges in today's integrated circuit (IC) designs create a significant increase in verification complexity. Read more of this whitepaper to learn how to go beyond the traditional triumvirate of DRC, LVS, and ERC to provide robust reliability verification throughout the design flow and ensure maximum design efficiency.

Spartan-6 FPGAs in Video Designs

In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.

Learn About Easier-to-Use Partial Reconfiguration Flow

Ever wonder whether the challenges of using partial reconfiguration are worth the benefits? Now, there's an easy-to-use, fine-grain partial reconfiguration methodology that delivers lower cost and power and higher system uptime. What's more, you don't need to understand the intricacies of FPGA architecture to get more usable density from your device.

Dynamic Power Reduction in Flash FPGAs

Due to the dramatic increase in portable and battery-operated applications, lower power consumption has become a necessity in order to prolong battery life. Power consumption is an important part of the equation determining the end product's size, weight, and efficiency. FPGAs are becoming more attractive for these applications due to their shorter product life cycle.

Versatile Digital QAM Modulator

Combined with enhanced DSP blocks, the logic structure of Altera’s Stratix® series and Arria® series FPGAs offer a flexible way to implement the key elements of the Quadrature Amplitude Modulation (QAM) signal-processing path in any region. With their innovative logic structure, enhanced dedicated DSP blocks, and the revolutionary memory blocks, Stratix series and Arria series FPGAs are perfect for cable head-end system designers who want flexibility and speedy time to market. In addition to these advanced features, Altera also provides an extensive set of IP cores and EDA tools to help simplify the design process.

Upgrade Your System's Resistive Touch Screen to Multi-Touch

With the introduction of cutting-edge touch screen products, the demand for multi-touch user-machine interfaces is growing. Adding multi-touch to a wide variety of products—from cell phones and MP3 players to medical imaging equipment and even washing machines—may be easier than you think. This webcast shows a very cost-effective way to add multi-touch to your system using Altera’s MAX® II CPLDs and surprisingly simple IP.

Empowering the Virtual Cluster

In this video, Nick Difiore explains how the capabilities of Xilinx FPGAs allow a switch from mechanical to electronic displays.

UAV-to-Basestation Encryption

Sr. Defense Architect Jim Anderson shows how Xilinx defense-grade Virtex FPGAs enable the highest level of information assurance with Type-1 Single-chip Cryptography in a UAV application.

SoC FPGA Product Overview Advance Information Brief

Altera's 28-nm Cyclone® V and Arria® V SoC FPGAs feature a hard processor system (HPS) containing a microprocessor unit (MPU) with a dual-core ARM® Cortex™-A9 MPCore™ processor, a rich set of peripherals, a multi-port memory controller, and FPGA fabric. The tight integration between the HPS and FPGA fabric supports over 100-Gbps peak bandwidth with integrated data coherency between the processors and the FPGA. The included set of hardened embedded peripherals eliminates the need to implement these functions in programmable logic, leaving more FPGA resources for application-specific custom logic. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP.

Next-Generation Packaging for CRM Applications

With smaller electronics, more options can be fit into the package, allowing for features such as RF transceivers for wireless communication, advanced sensors to optimally time pacing and defibrillation shocks and backup systems in case the main system fails. While integrated circuits (ICs) have taken advantage of advances in dense packaging, such as die stacking, in most cases the discrete components remain unchanged. Market pressures are now forcing improvements in the current discrete packaging.

Selecting the Ideal FPGA Vendor for Military Programs

As digital processing technologies such as digital signal processors, FPGAs, and CPUs become more complex and powerful, product and feature differentiation among vendors has significantly increased. As a result, designers need to develop rigorous approaches to evaluate the technologies available from different military defense electronics vendors.

Advanced Timing Exception Multicycle Path Constraints

Learn a little about the different types of exception constraints followed-up by a detailed look at the false path, min/max delay and case analysis constraints. We'll also review exception priority and a few tips for constraining exceptions constraints.

Xilinx and ARM: Zynq-7000 All Programmable SoC

Ian Ferguson, VP of Segment Marketing at ARM, introduces the Zynq®-7000 All Programmable SoC as the result of a strong partnership between ARM and Xilinx. He discusses how Zynq is opening up new markets for ARM and is alleviating the need for a multi-chip solution in many applications. Ferguson also speaks to Zynq's compatibility with leading operating systems and tools, and challenges designers to develop new and creative ways to design with a Zynq-7000 SoC.

Power Manager Pickle Power

This video is on the lighter side of Lattice. The Power Manager II family of devices integrates common, and some not-so-common, board power management functions into a single chip at half the cost.

OpenCL on FPGAs for GPU Programmers

In this white paper, Acceleware introduces parallel programming targeting Altera® FPGAs using the OpenCL™ framework to graphics processing unit (GPU) programmers. This white paper provides a brief overview of OpenCL, discusses the Altera FPGA architecture and its benefits, and explains how OpenCL kernels are executed and optimized on FPGAs versus GPUs.

9 Reasons Why The Vivado Design Suite Accelerates Design Productivity

Does your development team need to create complex, competitive, next-generation systems in a hurry? Download the new technical backgrounder and explore the 9 ways the Vivado® Design Suite improves your productivity.

Automating DSP Simulation and Implementation of Military Sensor Systems

Military sensor-driven systems normally use FPGAs to interface with the ADCs that digitize sensor inputs. Because ADCs operate at rates of up to 3 MSPS, they require very high-performance DSP circuitry. In most cases, this functionality is implemented using FPGAs optimized for DSP applications.


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register