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Meet PPA and Turnaround Time Requirements at Advanced Nodes with Innovus Implementation System

Today's complex IC designs demand a new generation of high-capacity, high-performance implementation tools. In this episode of Chalk Talk, Amelia Dalton chats Yufeng Luo of Cadence Design Systems about the incredible innovations in Cadence's new Innovus implementation suite.

From Simulation to Emulation – A Fully Reusable UVM Framework

This paper introduces an acceleration-ready UVM framework and explains why it is needed and how to create it. Readers will learn how to write block-level UVM environments that can be reused directly in emulation for block, subsystem, and system level verification. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Kintex UltraScale DSP Kit with 8 Lane JESD204B interface

The video highlights the Xilinx® Kintex® UltraScale™ FPGA Analog Devices JESD204B DSP Kit featuring the Xilinx Kintex UltraScale KCU105 development board with the KU40 device paired up with the Analog Devices AD-FMCDAQ2-EBZ high-speed analog FMC module. An 8 lane JESD204B interface is used to interface the data converters to the FPGA using GTX serial transceivers at the full 12.5 GSPS line rate. Xilinx devices are the world’s first to support the full JESD204B line rate across all device speed grades for mid-range JESD204B solutions, and the only all programmable solution available today at 20nm.

Connecting ZYNQ-7000 All Programmable SoCs with TE Connectivity Interconnect Products

New SoCs like the Xilinx Zynq are changing the industry - with new levels of functionality, flexibility, performance, and power efficiency. But, to take advantage of this new technology you'll need connectivity solutions that are up to the task. In this episode of Chalk Talk, Amelia Dalton chats with Mark Bell from TE Connectivity about plugs, connectors, antennas, and other connectivity solutions for today's most demanding designs.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

What’s New in PSpice 16.6

In this webcast Matthew Harms demonstrates the new features in version 16.6 of Cadence PSpice. Matthew covers three major areas: productivity enhancements, core enhancements, and TCL Integration. This webcast covers most of these features with an explanation and a short demonstration.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Sigrity PowerSI Tackles SSO Noise: Customer Success Story

AEI Systems needed to perform a worst case SSO analysis to screen their design and verify that defects and deficiencies would be eliminated prior to test, production and delivery. In doing so, they found that Cadence Sigrity PowerSI was the only tool tested that was able to provide the close correlation to the actual measurement needed to validate the RTAX board example. Click to see the process and results AEI Systems saw using Sigrity PowerSI to successfully evaluate worst case SSO noise.

Inductance-to-Digital Converters Revolutionize Position & Rotation Sensing

Inductive sensing is a reliable, accurate, and robust technology for a wide variety of position, rotation, metal detection and spring compression measurement applications. In this episode of Chalk Talk, Amelia Dalton chats with Anjana Govil of Texas Instruments about how you can use inductance-to-digital converters to take advantage for inductive sensing in your next design.

Accelerating Your Analog Output Design

Eventually, most of our designs need to control something in the real world. That means we have to bust out of our safe little digital realm, and drive some analog actuators or something similar. But, building that analog output section from scratch can be a real challenge. In this episode of Chalk Talk, Amelia Dalton talks to Bill Laumeister of Maxim Integrated about the Analog Output Design Accelerator Kit (MAXREFDES24EVSYS), a complete platform for easy evaluation that requires no lab equipment.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Debug This! Class-based testbench debugging with Visualizer

Rich Edelman says class-based debug is good news because it is not the same as debugging RTL. You don’t have to be an object-oriented programmer in order to debug a class-based testbench. Such a testbench just a bunch of objects – some statically created, some dynamic – which interact with the DUT. The upshot? Class based debug doesn’t have to be hard!

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

chalk talks

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Power Supply Management in High-Availability Systems

One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.

How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series)

In part 1 of this 3-part series, we talked about how you can save 75% on your next mixed-signal chip design - which was great, but we think we can do better than that. In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity even more. In this second epsiode of our 3-part Chalk TalkHD series, Amelia and Reid tell you how to save up to 99% on your design.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

latest papers and content

Meet PPA and Turnaround Time Requirements at Advanced Nodes with Innovus Implementation System

Today's complex IC designs demand a new generation of high-capacity, high-performance implementation tools. In this episode of Chalk Talk, Amelia Dalton chats Yufeng Luo of Cadence Design Systems about the incredible innovations in Cadence's new Innovus implementation suite.

Inductance-to-Digital Converters Revolutionize Position & Rotation Sensing

Inductive sensing is a reliable, accurate, and robust technology for a wide variety of position, rotation, metal detection and spring compression measurement applications. In this episode of Chalk Talk, Amelia Dalton chats with Anjana Govil of Texas Instruments about how you can use inductance-to-digital converters to take advantage for inductive sensing in your next design.

Connecting ZYNQ-7000 All Programmable SoCs with TE Connectivity Interconnect Products

New SoCs like the Xilinx Zynq are changing the industry - with new levels of functionality, flexibility, performance, and power efficiency. But, to take advantage of this new technology you'll need connectivity solutions that are up to the task. In this episode of Chalk Talk, Amelia Dalton chats with Mark Bell from TE Connectivity about plugs, connectors, antennas, and other connectivity solutions for today's most demanding designs.

Zynq-7000 All Programmable SoC: Embedded Design Tutorial

To help accelerate your Zynq®-7000 All Programmable SoC embedded development, Xilinx has introduced a new Embedded Design Tutorial, a hands-on guide designed to help walk you through embedded system design. The guide provides opportunities to work with tools under discussion, examples and an explanation of what is happening behind the scenes.

UltraFast Embedded Design Methodology Guide (REVISED)

Xilinx is building on the success of its UltraFast™ Design Methodology with the new UltraFast Embedded Design Methodology Guide. The new Guide enables embedded design teams to improve productivity with a documented methodology for the creation of smarter systems leveraging Zynq®-7000 All Programmable SoCs.

Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs

Xilinx discusses how programmable logic provides the partial reconfiguration capabilities, large number of high speed analog IOs and mix signal capabilities to build high density, scalable and flexible 500G/1T line cards today.

Xilinx and Ixia present 400GE and 25GE testing solutions at OFC 2015

In this live presentation from OFC 2015, Xilinx talks with Ixia about how they surmounted the many obstacles to efficient 400GE and 25GE testing by leveraging Xilinx’s All Programmable devices to get the Ixia 400GE and 25GE tester families to market quickly. Presented by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.

i.MX 6SoloX – Freescale’s New Heterogeneous Multicore Applications Processor

Many applications today need both an applications processor AND a real-time MCU. But, most solutions don't offer both on the same chip. In this episode of Chalk Talk, Amelia Dalton chats with Amanda McGregor of Freescale about a new application processor that combines an ARM Cortex-A9 core with the efficiency and real-time capability of the Cortex-M4.

UltraScale Integrated 100G Ethernet IP for 10x10G and 4x25G

This video demonstrates how using an integrated Ethernet MAC can save power, integration time and logic utilization while delivering the highest possible flexibility. The UltraScale™ Integrated 100G Ethernet IP supports both CAUI-4 and CAUI-10 interfaces to CFP, CFP2, CFP4 and other pluggable optics. As shown in this video, the IP can easily and dynamically swap between interfaces.

Kintex UltraScale DSP Kit with 8 Lane JESD204B interface

The video highlights the Xilinx® Kintex® UltraScale™ FPGA Analog Devices JESD204B DSP Kit featuring the Xilinx Kintex UltraScale KCU105 development board with the KU40 device paired up with the Analog Devices AD-FMCDAQ2-EBZ high-speed analog FMC module. An 8 lane JESD204B interface is used to interface the data converters to the FPGA using GTX serial transceivers at the full 12.5 GSPS line rate. Xilinx devices are the world’s first to support the full JESD204B line rate across all device speed grades for mid-range JESD204B solutions, and the only all programmable solution available today at 20nm.

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

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The UltraFast Design Methodology for the Vivado Design Suite

The UltraFast™ Design Methodology is a comprehensive design methodology enabling accelerated and predictable design cycles, delivered through the Vivado® Design Suite, a methodology guide, design checklist, self-training video, instructor-led courses, and third party tools & IP cores.

Microchip's Accessory Framework for Android(tm)

The Microchip's Accessory Framework for Android provides a mechanism to transfer data to and from an Android application through the USB of the microcontroller.

Industry's First DDR4 Controller and Interface Running at 2400 Mb/s

This demonstration showcases a DDR4 memory interface running at and above 2400 Mb/s with the Kintex® UltraScale™ FPGA. The memory interface will demonstrate adequate operating margin while running under stressful conditions, ensuring robust operation in the presence of voltage, process or temperature variation.

Unlock New Levels of Productivity for Your Design Using ISE Design Suite 12

In addition to the anticipated performance improvements commensurate with the production release of a Xilinx tool suite, the release of ISE v12 software unveils significant innovations with far-reaching potential. A new power-optimization capability called intelligent clock gating can reduce dynamic power by up to 30%. An innovation called design preservation vastly improves the user’s ability to achieve and maintain timing closure and design repeatability.

4 Steps to Bring Up a CFP2 Optical Module with a Virtex-7 HT FPGA

This video demonstrates the world's first all programmable heterogeneous FPGA interfacing to a CFP2 Optical Module. The demo walks through 4 steps required to bring up the system and then shows how Xilinx simplifies the integration process.

Software Debug Using Lauterbach TRACE32 on Veloce with Physical and Virtual Probes

This whitepaper discusses how the Lauterbach tools and Veloce emulator can work in both virtual and physical environments to give a consistent view for software debug. By connecting to either the virtual debug interfaces (used in models and simulators) or by connecting to physical debug hardware (used by FPGA prototypes and silicon), the Veloce emulator allows users to bridge the gap between the two environments, choosing the one applicable to their needs and position in the design flow.

Inductance-to-Digital Converters Revolutionize Position & Rotation Sensing

Inductive sensing is a reliable, accurate, and robust technology for a wide variety of position, rotation, metal detection and spring compression measurement applications. In this episode of Chalk Talk, Amelia Dalton chats with Anjana Govil of Texas Instruments about how you can use inductance-to-digital converters to take advantage for inductive sensing in your next design.

Scalable Smart Debugging With ZeBu-Server

In this episode of Chalk TalkHD, Amelia chats with Lauro Rizzatti of EVE about how EVE's ZeBu emulation technology can help you find that one last bug in even the biggest of designs.

Using the Vivado Timing Constraint Wizard

Learn how the timing constraints wizard can be used to “completely” constrain your design. The wizard adheres to the UltraFast™ design methodology defining your clocks, clock interactions, and finally your input and output constraints. In this video, you will see the wizard transform a partially constrained design into a fully constrained design that passes timing.

VeriSilicon and Cadence Customer Success Story

With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.

28Gbps Serial Transceiver Technology (HD 1920x1080)

Join Dr. Howard Johnson and Jack Carrel, Senior Staff Application Engineer from Xilinx as they review the new Virtex-7 HT FPGA family from Xilinx.

Meet PPA and Turnaround Time Requirements at Advanced Nodes with Innovus Implementation System

Today's complex IC designs demand a new generation of high-capacity, high-performance implementation tools. In this episode of Chalk Talk, Amelia Dalton chats Yufeng Luo of Cadence Design Systems about the incredible innovations in Cadence's new Innovus implementation suite.

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Choice of an ISA for Embedded Designs

Software investment is the biggest ticket item in any project. Hence the choice of an ISA that offers a scalable solution is an important consideration. MIPS and our SoC eco system offer distinct families of processor cores that span from 32-bit micro controllers all the way to 64-bit multi-threaded super-scalar cores from single-core to many cores, to address various segments of the embedded markets. For either a new design or a follow on or upgrade to an existing design, the choice of MIPS as the ISA offers an ideal path for protecting the software investment on a project, since one can scale the application up and down the performance scale seamlessly between a wide range of processors. The bulk of the effort in the migration to any new ISA is in the low-level initialization software. This paper illustrates the ease of migration from the ARM to MIPS architecture and highlight the areas that users need to focus on.

Industry’s 1st Single Chip 400GE Solution

Watch a demonstration of the industry’s first single chip solution for 400G applications, featuring the 20 nm Virtex® UltraScale™ device interfacing to Sumitomo Electric CFP4 optical modules and 10 km of optical fiber.

An Introduction to Rigid-Flex PCB Design Best Practices

More designers increasingly face project requirements for densely populated electronic circuits including pressures to reduce manufacturing times and costs. To meet these requirements, design teams have increasingly turned to 3D rigid-flex circuits to meet their project’s performance and production requirements.

MicroBlaze Overview

Learn basics of MicroBlaze™ such as key features, architecture and customization options. We'll also review some of the available MicroBlaze-based collateral.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.


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