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Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs

Xilinx discusses how programmable logic provides the partial reconfiguration capabilities, large number of high speed analog IOs and mix signal capabilities to build high density, scalable and flexible 500G/1T line cards today.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Xilinx and Ixia present 400GE and 25GE testing solutions at OFC 2015

In this live presentation from OFC 2015, Xilinx talks with Ixia about how they surmounted the many obstacles to efficient 400GE and 25GE testing by leveraging Xilinx’s All Programmable devices to get the Ixia 400GE and 25GE tester families to market quickly. Presented by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.

How to Waive DRC Results Using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Accelerating Your Analog Output Design

Eventually, most of our designs need to control something in the real world. That means we have to bust out of our safe little digital realm, and drive some analog actuators or something similar. But, building that analog output section from scratch can be a real challenge. In this episode of Chalk Talk, Amelia Dalton talks to Bill Laumeister of Maxim Integrated about the Analog Output Design Accelerator Kit (MAXREFDES24EVSYS), a complete platform for easy evaluation that requires no lab equipment.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

CircuitSpace 5.0: Discover Why Design Reuse Has Never Been Easier or More Flexible

This webinar is designed for Hardware Engineers and PCB Designers requiring an easy to use, flexible, and comprehensive design reuse methodology to coexist with their current OrCAD and Allegro PCB design tools. It is intended for new users as well as current users of EMA CircuitSpace software and focuses on front-to-back reuse methodologies and incorporates the new and enhanced features of version 5.0. Learn how the CircuitSpace 5.0 feature set can expedite your PCB layout process.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Mixed Signal Verification: The Long and Winding Road

Verification of your mixed-signal design can be a nightmare, with clashing disciplines and engineering cultures, and challenging use-case requirements. In this episode of Chalk Talk, Amelia Dalton chats with Steve Carlson of Cadence Design Systems about a comprehensive approach to mixed-signal system verification.

chalk talks

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Design @ MachXO2 Speed

Just about every design needs one - that magic, do-anything part that can connect nearly any two things together and can aggregate all those messy, left-over functions on our board. Today's low density PLDs have remarkable capabilities at a tiny cost and power budget. In this episode of Chalk Talk HD Amelia Dalton chats with Steve Hossner (Lattice Semiconductor) about the amazing capabilities of Lattice’s latest low density PLD line, the MachXO2.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Introducing SmartFusion2 FPGAs

In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about Microsemi's biggest FPGA announcement this year - SmartFusion2. This new family can do things we never expected from Microsemi's non-volatile FPGAs. Watch this Chalk Talk to learn what it's all about.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

latest papers and content

Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs

Xilinx discusses how programmable logic provides the partial reconfiguration capabilities, large number of high speed analog IOs and mix signal capabilities to build high density, scalable and flexible 500G/1T line cards today.

Xilinx and Ixia present 400GE and 25GE testing solutions at OFC 2015

In this live presentation from OFC 2015, Xilinx talks with Ixia about how they surmounted the many obstacles to efficient 400GE and 25GE testing by leveraging Xilinx’s All Programmable devices to get the Ixia 400GE and 25GE tester families to market quickly. Presented by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.

i.MX 6SoloX – Freescale’s New Heterogeneous Multicore Applications Processor

Many applications today need both an applications processor AND a real-time MCU. But, most solutions don't offer both on the same chip. In this episode of Chalk Talk, Amelia Dalton chats with Amanda McGregor of Freescale about a new application processor that combines an ARM Cortex-A9 core with the efficiency and real-time capability of the Cortex-M4.

UltraScale Integrated 100G Ethernet IP for 10x10G and 4x25G

This video demonstrates how using an integrated Ethernet MAC can save power, integration time and logic utilization while delivering the highest possible flexibility. The UltraScale™ Integrated 100G Ethernet IP supports both CAUI-4 and CAUI-10 interfaces to CFP, CFP2, CFP4 and other pluggable optics. As shown in this video, the IP can easily and dynamically swap between interfaces.

Kintex UltraScale DSP Kit with 8 Lane JESD204B interface

The video highlights the Xilinx® Kintex® UltraScale™ FPGA Analog Devices JESD204B DSP Kit featuring the Xilinx Kintex UltraScale KCU105 development board with the KU40 device paired up with the Analog Devices AD-FMCDAQ2-EBZ high-speed analog FMC module. An 8 lane JESD204B interface is used to interface the data converters to the FPGA using GTX serial transceivers at the full 12.5 GSPS line rate. Xilinx devices are the world’s first to support the full JESD204B line rate across all device speed grades for mid-range JESD204B solutions, and the only all programmable solution available today at 20nm.

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

SDSoC Development Environment: Estimation & Implementation

Part 1 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews the challenges in implementing a system in a Zynq® SoC device and how SDSoC helps resolve those challenges. Then the video shows a demo of SDSoC on an example design to generate performance estimate and run a full design implementation using those estimates, and verifying the results achieved on the evaluation board.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

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Xilinx SDNet: A New Way to Specify Network Hardware

This paper, written by The Linley Group, examines Xilinx’s SDNet specification environment and its role, both in defining elements in Software-Defined Networks, and in implementing reconfigurable network elements in both control plane and data plane.

Xilinx Agile Mixed Signal

In this episode of Chalk TalkHD Amelia chats with Steve Logan (Xilinx ) and they're going to tell you all about Agile Mixed Signal, and how it can dramatically improve the capabilities of your next FPGA design.

Hardware Programmability

Learn how FPGAs allow you to customize for your specific needs while enabling you to protect your differentiation in the marketplace.

OrCAD Constraint Driven Design Flow

The OrCAD constraint driven flow provides a unique, fully integrated environment to define design intent and dynamically track compliance throughout the entire implementation process. This slideshow is demonstrating how to utilize the constraint driven flow in OrCAD to improve efficiency, reduce errors, and help ensure on-time product delivery.

UltraFast Vivado Design Methodology For Timing Closure

The methodology outlined in this training will enable you to achieve “Sign-Off” quality XDC constraints for timing closure. This methodology will also enable you to achieve timing closure significantly faster irrespective of the complexity of the design.

Xilinx Documentation Navigator Overview

The Xilinx Documentation Navigator helps customers find the information they need quickly, ensures customers are always reading the latest information, and offers single-click download management. This short video provides an overview of the Xilinx Documentation Navigator.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Injecting Automation into Verification - FPGA Market Trends

This webinar is a manager’s introduction to trends in the FPGA market and provide a business perspective on how companies are crossing the FPGA design verification barrier. Learn the common tools, techniques and learning aids that make an effective FPGA verification process. We will discuss the business and technical merits of common techniques and processes that your team can start deploying now.

Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Pattern Matching:  Blueprints for Further Success

Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process.

OrCAD Data Management & Collaboration

Learn how EMA and Cadence are enabling the next generation of engineering data management workflows. This presentation will take you through a complete methodology covering design data management, component library management with automated footprint and symbol creation, and team based schematic design. These OrCAD engineering data management design technologies are geared to provide designers with purpose built tools to effectively manage your PCB data right from within your OrCAD design environment.

Cadence and IBM: Customer Success Story

“The Cadence solution enables us to enter up to 99 percent of signals in table format, which, along with improved analytics and a unique integrated environment, reduced our PCB development time by 80 percent.” Learn why Gisbert Thomke, a group leader at IBM is able to say that and how exactly the company accelerates large-scale PCB system design using unique cadence multi-style design entry solution.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

New Episode - Design Starts and Revisions - Designing With Altium Series

Find out more about Altium Designer, Altium’s development of Vault-Driven Electronics Design and Designing with Altium by watching this video series.

How to select specific rule checks for a Calibre DRC run

This video shows you how to create specific rule check recipes for running DRC in Calibre Interactive. Rule check recipes allow you to configure and reuse specific rule checks such as metal, density, and antenna checks across multiple Calibre DRC jobs. This will reduce the runtime for your Calibre DRC jobs and allows you to focus on the Calibre DRC results that you want to fix.


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