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A Methodology to Manage Mechatronic Development in Medical Electronic Products

Model Driven Development (MDD) dramatically reduces the risks of complex mechatronic system development, increases productivity within an FDA-regulated process, and automates collaborative development among disparate teams. An MDD flow gives the system integrator an effective platform from which to communicate the overall system requirements and can also tie project management into development and automate mundane/time-consuming tasks, so designers can spend their time doing what they do best – designing.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Hardware in the Loop from the MATLAB/Simulink Environment

This white paper describes the tools, design flow, and verification of systems using Altera(r) FPGAs. It discusses the techniques of software simulation and hardware testing, and the challenges associated with them. This paper also describes the advantages of using the Hardware in the Loop (HIL) tool, which is part of Altera's software tools, to simplify software simulation and hardware testing in a variety of applications.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Security Aspects of Lattice Semiconductor iCE40 Mobile FPGA Devices

Product piracy is of strong concern to major companies around the world. R&D costs are very high for leading companies. Therefore, companies plan to recoup these R&D costs by sale of their proprietary products. If pirates are able to steal or copy the final design, or countermand the security systems of these proprietary products, the market will become flooded with low cost alternatives. As a final consequence, major companies will find themselves unable to recover their high development costs, and will lose valuable profits.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

Solving the ASIC Prototype Partition Problem with Synopsys ProtoCompiler

When developing a multi-FPGA prototype of an ASIC or SOC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules should be assigned to each FPGA; where and how many cables connect the FPGAs; and how to squeeze all the signals into those cables. All these decisions need to result in the fastest possible prototype that you can build and debug in the allotted time. And every week the RTL changes, and sometimes it seems that every decision you make forces you to revisit all the decisions that came before.There is a better way.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

USB Controller Connectivity

In this week's Whiteboard Wednesday video, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC), and how they improve connectivity between multiple USB applications. Learn more about Cadence IP at http://ip.cadence.com.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

chalk talks

Spartan-6 FPGAs in Video Designs

In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Integrated Design Environment for FPGA

Do you find that FPGA design flows can get a bit confusing and difficult to manage? What we really need is an integrated design environment that will help us keep our design activities organized. In this episode of Chalk TalkHD Amelia chats with Satyam Jani from Aldec about integrated design environments (IDEs) for FPGA design, why FPGA designers need a vendor-independent IDE, and how an FPGA-centric IDE can help us get through our design flow quite a bit more easily.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.

IP and Process Solutions for Energy-efficient PMICs

In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

latest papers and content

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

USB Controller Connectivity

In this week's Whiteboard Wednesday video, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC), and how they improve connectivity between multiple USB applications. Learn more about Cadence IP at http://ip.cadence.com.

A Methodology to Manage Mechatronic Development in Medical Electronic Products

Model Driven Development (MDD) dramatically reduces the risks of complex mechatronic system development, increases productivity within an FDA-regulated process, and automates collaborative development among disparate teams. An MDD flow gives the system integrator an effective platform from which to communicate the overall system requirements and can also tie project management into development and automate mundane/time-consuming tasks, so designers can spend their time doing what they do best – designing.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Faster Wiring and Harness Design

Does your electrical design software just do the basics? Or does it take the complexities of today's designs out of the task and save you time and money? This short white paper outlines the top ten highlights of how new tools make wiring and harness design faster and better.

EWIS Requirements: The Business Challenge

Without proper planning and the evolution of their business to efficiently deal with the EWIS mandates, companies could find themselves in a very costly situation. This paper investigates the issues surrounding EWIS compliance and methods to minimize both cost and potential program delays.

EDS Design Tools for Electric Vehicles

This paper explores how challenges for electric vehicles from battery placement to electrical distribution to eliminating crosstalk between high- and low-level signals can be solved with advanced EDS software. Also see how design environments incorporate features for designer to address product plans and answer tomorrow's demand for fully electric vehicles.

Injecting Automation into Verification – Improved Throughput

This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

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Xilinx and ARM Address New Markets

Ian Ferguson, VP of Segment Marketing at ARM, explains how an ARM processor combined with an FPGA addresses the embedded space. He also discusses three areas where programmable logic provides the most value along with the new markets addressed by the Zynq®-7000 All Programmable device.

SDNet Overview with VP Nick Possley

Xilinx Vice President Nick Possley discusses how the new Software Defined Specification Environment for Networking (SDNet) is enabling 'Softly' Defined Networks, what benefits it's bringing to system architects and why it's considered revolutionary.

National Instruments Comments on Xilinx Extensible Processing Platform

Xilinx Extensible Processing Platform testimonial from customer National Instruments.

Xilinx Redefines Power, Performance, and Design Productivity with Three New 28 nm FPGA Families:Virtex-7, Kintex-7, and Artix-7 Devices

Three new Xilinx product families leverage the unprecedented power, performance, and capacity enabled by TSMC's 28 nm high-k metal gate (HKMG), high performance,low power (HPL) process technology and the unparalleled scalability afforded by the FPGA industry's first unified silicon architecture to provide a comprehensive platform base for next-generation systems. Watch this webcast to learn more.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Smarter Solutions for Wireless Networks

Chief DSP Architect—Chris Dick—Describes some of the biggest challenges facing the mobile industry today and how customers address it with Xilinx's All Programmable devices.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

5 Reasons to Put Your Processor on an FPGA

Did you know that soft-core FPGA processors provide unique benefits that you can’t achieve with commercial off-the-shelf systems? Learn five reasons why you should put your processor on an FPGA. Watch this 9-minute video to get more details on: Design flexibility, with a customizable peripheral set, Protection against processor obsolescence, Multi-core support, Hardware acceleration, Familiar software tools.

MediaTek Gets High-Quality Smart Devices to Market Quickly with Palladium Platform

In this video, Andrew Chang, MediaTek corporate vice president, talks about the challenges in creating today's smart devices—complexity, the push for higher performance, and the need for lower power. Chang discusses how the Cadence® Palladium® platform has helped MediaTek achieve faster simulation and debug; the company has achieved a 300X speed-up in simulation time, with 6X faster turnaround time. As a result, MediaTek is succeeding in meeting its time-to-market and design quality goals.

Developing Functional Safety Systems with TÜV-Qualified FPGAs

Market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs.

Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!

Easily Create PCIe-Based Designs for FPGAs

When implementing high-bandwidth PCI Express® (PCIe®) designs on FPGAs, success is never guaranteed. You want to spend your time creating custom logic that differentiates your design in the marketplace, not doing tedious work like manually wiring up all the components. Get your design to market faster and with less effort by using tools that free you up to complete the creative design work. These innovations will help you avoid the complexities of PCIe implementation, such as Transaction Layer Packet encoding and decoding, along with the mundane tasks of system integration like width matching, clock domain conversion, and arbitration. This way, you can dramatically shorten your FPGA design and verification cycles, meet performance requirements, and increase your overall design productivity.

Virtex-7 2000T FPGA for ASIC Prototyping & Emulation

Watch this video to learn how a complex SoC platform was mapped into a single Virtex®-7 2000T FPGA, the world's largest 3D IC in volume production. With well over 2 million logic cells, the Virtex-7 2000T reduces the need for design partitioning and simplifies the mapping of ASIC RTL. This breakthrough capacity coupled with Xilinx's Next Generation Vivado™ Design Suite provides the ideal solution to tackle the demands of leading edge ASIC and SoC devices.

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays video, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses specs for USB 2.0 and USB 3.X in detail.

Optimize Power and Cost with Altera’s Diversified 28nm Device Portfolio (REVISED)

Altera’s 28-nm devices provide a diversified product portfolio tailored to support a broad spectrum of applications, ranging from low cost and power, to high-end applications. This white paper describes the power and cost advantages of Altera’s Stratix® V, Cyclone® V, Arria® V, and HardCopy® V devices.

Xilinx 4x100G Transponder Reference Design

Learn about Xilinx's 4x100G Transponder Reference Design running on the VC730 OTN Test Development Platform.

Compiling, Installing, and Running MIPS NDK Native Applications

Are you working on Android apps development? This app note on the MIPS NDK describes how to build Android applications in native C or C++.


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