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Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Market-Specific Custom IC Solutions

When it comes to custom IC design, one size most definitely does not fit all. Different applications call for specialized IP, tools, and even semiconductor processes. But, sorting through the options can be a daunting process. In this episode of Chalk Talk, Amelia Dalton chats with Pavel Klinger from GLOBALFOUNDRIES about market-specific solutions that can get your product to market faster and with lower risk than ever.

The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include ARM AMBA 4, ARM AMBA 5, OCP, DDR, LPDDR, LPDDR3, LPDDR4, Wide I/O, Wide I/O2, DRAM, eMMC, eMMC5, UFS, CSI-3, SoundWire, USB, PCIe, and SSIC.

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User’s Guide

This demo design shows SmartFusion®2 SoC FPGA device capabilities for code shadowing from serial peripheral interface (SPI) flash memory to single data rate (SDR) synchronous dynamic random access memory (SDRAM) and executing the code from SDR SDRAM. Code shadowing is a booting method that is used to execute an image from external faster volatile memories (DRAM) and is the process of copying the code from nonvolatile memory to volatile memory for execution. In performance critical applications, execution speed can be improved by code shadowing where code is copied to higher throughput RAM for faster execution.

Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays video, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses specs for USB 2.0 and USB 3.X in detail.

OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications

This joint white paper by MTI Mobile and Altera presents a proof of concept implementation of digital baseband radio data transport over Optical Transport Network (OTN) compliant to 3GPP Long Term Evolution – Advanced (LTE-A) standard, which enables us to exploit the benefits of Cloud Radio Access Network (C-RAN) architecture. The purpose of this paper is to demonstrate that data transport between the MTI Radiocomp’s baseband module and a remote radio module over an OTN-compliant mapper from Altera is compliant to Common Public Radio Interface (CPRI) and to the OBSAI interface protocols.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Introducing Digitally Enhanced Power Analog

Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.

How To Save 75% on Your Next ASIC Design

Do you think developing a custom mixed-signal chip for your application is beyond your team's reach? Too expensive, complicated, and risky? Think again! In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity - bringing that custom chip design within reach. In part one of our three-part Chalk TalkHD series, Amelia and Reid tell you how to save 75% on your design.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Using Low Cost, non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

chalk talks

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

GLOBALFOUNDRIES RFCMOS Solutions and Catena WiFi Solutions

In this episode of Chalk TalkHD Amelia Dalton chats with Fayyaz Singaporewala (GLOBALFOUNDRIES) and Mats Carlsson (Catena) about how to get that scary RF portion of your next design done in a snap.

It's 2022: Do You Know What Your FPGA Is?

Does the definition of "FPGA" seem like a moving target? Over the past few years, there has been phenomenal progress in FPGA technology - going from simple glue logic to impressive programmable systems-on-chip. Today's FPGAs are some of the most powerful and flexible devices ever built. But, what will your FPGA look like ten years from now? In this episode of Chalk TalkHD Amelia Dalton chats with Umar Mughal of Altera about the past, present, and future of this exciting technology.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

latest papers and content

Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays video, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses specs for USB 2.0 and USB 3.X in detail.

Comparing 3D Memory Solutions and Their Market Applications

In this week's Whiteboard Wednesdays video, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions available today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott took a closer look at 2D memory solutions like EMMC 5.0, UFS, and DDR4.

How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources. Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

Artix-7 FPGA Transceiver: The Industry's Most Capable Transceiver in a Low-End Device

In this video you’ll see the FPGA industry’s only low end transceiver solution—the Artix-7 FPGA transceiver—that provides auto-adaptive equalization, 2D Eye Scan, and IBIS-AMI simulation models to simplify high speed serial design for cost-sensitive applications.

Xilinx Broadest Cost Effective All Programmable Low-end Portfolio

This generation of all programmable, cost-sensitive applications has reached new levels of sophistication and diversity of requirements. Low cost systems in the consumer, automotive, industrial, medical, and communications space may need a programmable logic device with high serial bandwidth, or for advanced processing, or may simply need bridging functionality and little else. Commonly termed the “low-end” market due to the devices’ relatively low cost and density, these platforms provide varying levels of system integration, performance, and power. They may perform critical tasks such as video analytics or packet processing, or simply expand a system’s I/O connectivity to peripheral devices.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Using Low Cost, non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs. These challenges can easily be overcome with the use of FPGAs (field programmable gate arrays), which over the past 10 years have seen a significant reduction in cost and power consumption, making them ideal for a wide range of high- volume, low-cost applications including mobile.

Security Aspects of Lattice Semiconductor iCE40 Mobile FPGA Devices

Product piracy is of strong concern to major companies around the world. R&D costs are very high for leading companies. Therefore, companies plan to recoup these R&D costs by sale of their proprietary products. If pirates are able to steal or copy the final design, or countermand the security systems of these proprietary products, the market will become flooded with low cost alternatives. As a final consequence, major companies will find themselves unable to recover their high development costs, and will lose valuable profits.

Vivado IP Integrator - Tech Packet

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design.

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Simpler, Smarter Platform for Differentiated Digital TVs

The Spartan-6 FPGA Consumer Video kit provides a simpler way to update and modify video algorithms, and incorporate new video standards such as DisplayPort and V-by-One-HS. The advanced integrated design environment allows designers to efficiently develop and test high speed serial interfaces like LVDS and TMDS and debug HDMI or DVI-based solutions. The Spartan-6 FPGA Consumer Video Kit offers everything designers need to implement features for today and tomorrow's market. Watch this short video to learn more.

Using 10-Gbps Transceivers in 40G/100G Applications (REVISED)

This white paper identifies the drivers behind the migration to 100G interfaces, and shows how to leverage FPGAs to implement this high-speed interface. The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. In addition to providing an unprecedented amount of resources such as logic, on-chip memory, and DSP blocks, Altera Stratix IV devices are the only FPGA family to enable these designs.

Parameterizable Content-Addressable Memory

This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software. The CAM reference design should be used for all new FPGA designs targeting Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP FPGAs, and newer architectures. All the features and interfaces included in the reference design are backward compatible with the LogiCORE™ IP CAM v6.1 core. In addition, because the reference design is provided in plain-text VHDL format, the implementation of the function is fully visible, allowing for easy debug and modification of the code.

Lower Power and Boost System Bandwidth on 28nm FPGAs

It’s a challenging balancing act to meet growing bandwidth demands without increasing cost or power consumption. And it’s probably a challenge you know well if you’re designing high-end systems in areas such as communications, broadcast, military, and computer/storage. Achieve the right balance with Altera’s Stratix® V FPGAs, which deliver breakthrough bandwidth, reduced cost, and the lowest total power.

Learn How Dev Kit Utilities Shorten the Design Process

Are you looking for a way to speed up the design process for your low-power FPGA applications? This 10-minute video will give you a closer look at the Cyclone® III LS FPGA Development Kit, particularly two utilities that accelerate the design cycle – the Board Test System and the Board Update Portal. You'll see the Cyclone III LS FPGA Development Kit in action and find out how this device can support your cost-sensitive, bandwidth-intensive applications.

Gate-Level Simulation Methodology

It is critical that teams begin GLS as early in the design cycle as possible, that the simulator run in high-performance mode, and that a proven simulation methodology be in place. This white paper explores new simulator use models and methodologies that boost GLS productivity, including extraction via static timing analysis and linting. Using these approaches, designers can focus on verifying real gate-level issues rather than waste expensive simulation cycles on re-verifying working circuits.

Security Aspects of Lattice Semiconductor iCE40 Mobile FPGA Devices

Product piracy is of strong concern to major companies around the world. R&D costs are very high for leading companies. Therefore, companies plan to recoup these R&D costs by sale of their proprietary products. If pirates are able to steal or copy the final design, or countermand the security systems of these proprietary products, the market will become flooded with low cost alternatives. As a final consequence, major companies will find themselves unable to recover their high development costs, and will lose valuable profits.

City Semiconductor—Cadence Hosted Design Solutions Helps Tapeout Analog-to-Digital Converter

Chris Menkus, Founder and CEO, City Semiconductor, outlines the benefits of using the solid support and collaboration technology found in Cadence(r) Hosted Design Solutions’ environment to create their new high-speed 12-bit Analog to Digital Converter.

MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 LUTs. In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM, Distributed RAM, User Flash Memory, PLLs, pre-engineered source synchronous I/O support and hardened versions of functions such as SPI controller, I2C controller and timer/counter. These devices are ideal for low cost, high volume consumer and system applications.

LatticeECP3 FPGA Jamz Music Video

If you enjoyed the original Lattice MachXO2 "pitchman" video in 2010, or the follow-up Power Manager II "pickle" video, check out the latest music video from Lattice featuring the LatticeECP3 FPGA. It's not surprising that when you mix a great product like the LatticeECP3 with a light-hearted video, the response is going to be win-win for an engineering audience.

Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions

Because a fast and robust memory interface is crucial for many designers, Altera provides the fastest, most efficient, and lowest latency memory controllers, which allow designers to work with today’s higher speed memories quickly and easily. Designing with Arria V FPGAs not only helps to make designs successful but also ensures that implementation is fast and easy.

Introducing VTOS for Embedded Hardware Verification

An environment for functional testing, peeking and poking memory, bus discovery and a powerful scripting because today’s embedded hardware design tools do not address the design test and verification process for prototype hardware, hardware engineers are forced to resort to in-house tools or application OS based testing, resulting in poor test coverage. This paper presents a new hardware test and verification process, based on a Verification and Test OS (VTOS™). VTOS is a user configurable test platform, requiring no porting and can be testing new prototype hardware in 30 minutes. VTOS provides an environment that includes functional tests, peeking and poking memory mapped locations, bus discovery and a powerful scripting language.

Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk

High-Level Synthesis (HLS) has many benefits for integrated circuit design but also introduces challenges for integration into SoCs. This paper proposes solutions that improve HLS system integration by eliminating manual interface specification, reducing debug and allow system integration and verification tasks to be performed earlier. By enabling an HLS to SoC flow from a model-based design environment, these methods increase productivity and eliminate manual effort, errors and risk.

A Significant Technology Advancement in High-Speed Link Modeling and Simulation

As high-speed I/O (HSIO) and serial link data rates keep increasing, the requirements for accuracy and advanced simulation and modeling techniques get more stringent. This white paper reviews the techniques used in recent HSIO simulation and modeling, such as statistical behavioral, SPICE, and IBIS-AMI models, outlining the areas where they fall short in comparison with the emerging requirements. This paper also introduces Altera's JNEye transceiver link simulation tool and discusses how the tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the emerging requirements.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Mixed-Signal Power Management: Bridging the Analog-Digital Divide with Mixed-Signal FPGA Graphical Design Configuration Methodology

The management of power at the system level is a challenge faced by all system designers, but designers face a daunting divide between digital and analog when considering tools, practices, and methodologies. A new methodology developed by Actel, implemented in a new design tool, addresses the challenges, and eliminates barriers to delivering user-configurable mixed-signal power management without the need to reprogram circuit design changes to implement configuration changes.

9 Reasons Why The Vivado Design Suite Accelerates Design Productivity

Does your development team need to create complex, competitive, next-generation systems in a hurry? Download the new technical backgrounder and explore the 9 ways the Vivado® Design Suite improves your productivity.

System Management

Semiconductor devices are prone to failure even after they have been tested, packaged and shipped by the semiconductor vendor. The main factors that contribute to device failure in a system are electrically, environmentally and mechanically induced failures. Because mechanical failures are almost impossible to mitigate at the electrical or electronic design stage the following discussion focuses on electrical and environmental stresses.


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