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Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Xilinx Broadest Cost Effective All Programmable Low-end Portfolio

This generation of all programmable, cost-sensitive applications has reached new levels of sophistication and diversity of requirements. Low cost systems in the consumer, automotive, industrial, medical, and communications space may need a programmable logic device with high serial bandwidth, or for advanced processing, or may simply need bridging functionality and little else. Commonly termed the “low-end” market due to the devices’ relatively low cost and density, these platforms provide varying levels of system integration, performance, and power. They may perform critical tasks such as video analytics or packet processing, or simply expand a system’s I/O connectivity to peripheral devices.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

Comparing 3D Memory Solutions and Their Market Applications

In this week's Whiteboard Wednesdays video, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions available today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott took a closer look at 2D memory solutions like EMMC 5.0, UFS, and DDR4.

OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications

This joint white paper by MTI Mobile and Altera presents a proof of concept implementation of digital baseband radio data transport over Optical Transport Network (OTN) compliant to 3GPP Long Term Evolution – Advanced (LTE-A) standard, which enables us to exploit the benefits of Cloud Radio Access Network (C-RAN) architecture. The purpose of this paper is to demonstrate that data transport between the MTI Radiocomp’s baseband module and a remote radio module over an OTN-compliant mapper from Altera is compliant to Common Public Radio Interface (CPRI) and to the OBSAI interface protocols.

Introducing Digitally Enhanced Power Analog

Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Fast, Efficient RTL Debug for Programmable Logic Designs

In a typical FPGA design flow, most designers work from a written specification that contains architectural level drawings defining the major logic blocks, interfaces, and busses. The design manager begins to partition functionality based on the diagrams and to assign development based on the block’s functional descriptions. Each block is coded individually and may be simulated in a block-specific test bench. The team assembles the blocks into a device-level file where the ports are pins on the target device. The design is then ready to be compiled for simulation initiating the debug phase of development: Simulation followed by hardware debug.

How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series)

In part 1 of this 3-part series, we talked about how you can save 75% on your next mixed-signal chip design - which was great, but we think we can do better than that. In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity even more. In this second epsiode of our 3-part Chalk TalkHD series, Amelia and Reid tell you how to save up to 99% on your design.

Artix-7 FPGA Transceiver: The Industry's Most Capable Transceiver in a Low-End Device

In this video you’ll see the FPGA industry’s only low end transceiver solution—the Artix-7 FPGA transceiver—that provides auto-adaptive equalization, 2D Eye Scan, and IBIS-AMI simulation models to simplify high speed serial design for cost-sensitive applications.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

FPGA Product Support and EOL as Past Performance Indicators

This white paper presents the factors that lead to product obsolescence decisions made by FPGA vendors and how you can use this knowledge to craft obsolescence risk mitigation plans. This paper also introduces the idea of exercising Past Performance Assessments of FPGA vendors as both a risk and cost factor in making FPGA selection in military system design.

World's Smallest FPGAs Solve 4 Big Problems

In this episode of Chalk Talk, Amelia chats with Gordon Hands (Lattice Semiconductor) about some awesomely tiny FPGAs that bring the power of programmable logic into devices like cell phones, tablets, and other power and form factor sensitive applications.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

chalk talks

Maximizing Battery Life with TI's Wolverine Technology

In this episode of Chalk TalkHD Amelia chats with Ryan Hoium (Texas Instruments) about about TI’s revolutionary Wolverine technology and a new series of ultra-low power MCUs that will change the way we think about batteries in our embedded designs.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Vault-Driven Electronics Design

In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how to set up a robust design-for-re-use design methodology for your team that will flow nicely with your project, won’t take much effort to set up, and will bring BIG TIME long-term benefits of design re-use, configuration management, and manufacturing handoff.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

latest papers and content

Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays video, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses specs for USB 2.0 and USB 3.X in detail.

Comparing 3D Memory Solutions and Their Market Applications

In this week's Whiteboard Wednesdays video, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions available today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott took a closer look at 2D memory solutions like EMMC 5.0, UFS, and DDR4.

How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources. Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

Artix-7 FPGA Transceiver: The Industry's Most Capable Transceiver in a Low-End Device

In this video you’ll see the FPGA industry’s only low end transceiver solution—the Artix-7 FPGA transceiver—that provides auto-adaptive equalization, 2D Eye Scan, and IBIS-AMI simulation models to simplify high speed serial design for cost-sensitive applications.

Xilinx Broadest Cost Effective All Programmable Low-end Portfolio

This generation of all programmable, cost-sensitive applications has reached new levels of sophistication and diversity of requirements. Low cost systems in the consumer, automotive, industrial, medical, and communications space may need a programmable logic device with high serial bandwidth, or for advanced processing, or may simply need bridging functionality and little else. Commonly termed the “low-end” market due to the devices’ relatively low cost and density, these platforms provide varying levels of system integration, performance, and power. They may perform critical tasks such as video analytics or packet processing, or simply expand a system’s I/O connectivity to peripheral devices.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Using Low Cost, non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs. These challenges can easily be overcome with the use of FPGAs (field programmable gate arrays), which over the past 10 years have seen a significant reduction in cost and power consumption, making them ideal for a wide range of high- volume, low-cost applications including mobile.

Security Aspects of Lattice Semiconductor iCE40 Mobile FPGA Devices

Product piracy is of strong concern to major companies around the world. R&D costs are very high for leading companies. Therefore, companies plan to recoup these R&D costs by sale of their proprietary products. If pirates are able to steal or copy the final design, or countermand the security systems of these proprietary products, the market will become flooded with low cost alternatives. As a final consequence, major companies will find themselves unable to recover their high development costs, and will lose valuable profits.

Vivado IP Integrator - Tech Packet

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design.

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Understanding the Impact of Single Event Effects in Networking Applications

Reliability of communication is essential in networking applications. The goal of five nines (99.999%) in network availability translates to less than six minutes in downtime in a year for the entire network. Among the many impacts on system reliability are the effects of ionizing radiation on electronic circuits. This radiation can cause memory elements in electronic circuits to change state. When this happens in the configuration memory of SRAM-based FPGAs, it can cause a change in the functionality of the circuit, greatly impacting system reliability. Designers of networking applications must understand the effect of this radiation and how to reduce the risk to the network.

Overcome Design Challenges with an Innovative IP Scalability, Integration, and Delivery Model

Intellectual property (IP) is a key component in system designs for many different end markets. This white paper explores how Altera and partner IP solutions can provide the differentiation you need for your next-generation applications. This white paper examines the feasibility of developing IP in-house or buying from a third party, and also presents Altera's innovative IP scalability, integration, and delivery model. With this model, Altera not only simplifies the process of acquiring, evaluating, testing, and integrating IP into your design, but also mitigates the risks of using third-party IP.

Solutions for Mixed-Signal SoC Verification

As SoC complexity grows and process nodes shrink, it’s no longer adequate to bolt together analog or digital “black boxes” that are presumed to be pre-verified. Complex analog/digital interactions can create functional errors, which delay tapeouts and lead to costly silicon re-spins. Cadence helps customers overcome these challenges with a fully integrated mixed-signal verification solution that spans basic mixed-signal simulation to comprehensive, metric-driven mixed-signal verification.

Power Supply Transients on RTAX-S and RTSX-SU Devices

Single-event effects (SEE) during operation of power regulators can cause the output of the regulator to be as high as the regulator input for short durations, on order of tenths of microseconds. Consequently, any device that is powered by the regulator could see this supply glitch during normal operation of the device. This report summarizes the experiments and data collected to study the impact of these power supply glitches on the RTAX™-S and RTSX-SU devices on printed circuit boards.

Using Low Cost, Non-Volatile PLDs in System Applications

Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in system applications. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to-market, address system cost and space reduction, and ensure a high level of product differentiation.

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

Designing for Low Power

FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3’s static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs.

Enabling New Applications with NFC Connectivity and Energy Harvesting

In this episode of Chalk TalkHD Amelia chats with Greg Proehl (STMicroelectronics) about the basics of NFC technology, and they explore some interesting NFC applications as well as cool and innovative new NFC solutions from ST - including one with energy harvesting capability.

Learn to Design at MachXO2 Speed!

The MachXO2 family of programmable logic devices is optimized for low density applications, with an unprecedented mix of low cost, low power and high system integration. Now, with 10 new reference and demo designs, you can complete your design faster than ever. Check out our new live seminars.

Virtex-6HXT Lab Demo

This video shows a quick lab demo of the Virtex-6HXT, the industry's highest bandwidth FPGA, featuring 24GTH transceivers (11+Gb/s) AND GTX transceivers (6.6Gb/s) for a total of 72 Transceivers. This FPGA combines the world's highest performance FPGA fabric with the world's highest performance serial transceivers, sampling now! Please subscribe and stay tuned for future demos of our superior performance and exclusive compliance to a variety of optical specs.

Freescale Utilizes the Cadence Low-Power and Mixed-Signal Solutions to Verify Kinetis Products

Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence® Low-Power and Mixed-Signal Solution to verify the company’s Kinetis Microcontroller products targeted for automotive and internet-of-things applications.

Reducing Cost and Power in Consumer Applications Using PLDs

The need to respond to changing market standards in a compressed time to market window has led to the widespread use of programmable logic devices (PLDs) in a broad range of consumer applications. Unlike ASICs and ASSPs, PLDs do not require long lead times: their functionality can be changed at any time to accommodate a change in product requirements. In many market segments, such as handheld devices, PLDs have found acceptance due to new product architectures that reduce power consumption, feature new packaging options and lower unit cost.

SmartFusion2 Product Brochure

Microsemi's next-generation SmartFusion2 SoC FPGAs are the only devices that address fundamental requirements for advanced security, high reliability and low power in critical industrial, military, aviation, communications and medical applications. SmartFusion2 integrates an inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM® Cortex™-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM, and industry-required high-performance communication interfaces all on a single chip.

SmartFusion Customizable System-on-Chip: Intelligent, Innovative Integration

The whole point of an FPGA is flexibility. We could also mention integration and say instead that the whole point of an FPGA is flexibility and integration. But then there is cost savings. So the whole point of an FPGA is flexibility, integration and cost savings. Yet there is also power reduction. And then there’s security.

MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 LUTs. In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM, Distributed RAM, User Flash Memory, PLLs, pre-engineered source synchronous I/O support and hardened versions of functions such as SPI controller, I2C controller and timer/counter. These devices are ideal for low cost, high volume consumer and system applications.

Xilinx Redefines Power, Performance, and Design Productivity with Three New 28 nm FPGA Families:Virtex-7, Kintex-7, and Artix-7 Devices

Three new Xilinx product families leverage the unprecedented power, performance, and capacity enabled by TSMC's 28 nm high-k metal gate (HKMG), high performance,low power (HPL) process technology and the unparalleled scalability afforded by the FPGA industry's first unified silicon architecture to provide a comprehensive platform base for next-generation systems. Read this whitepaper to learn more.

A Platform for Reducing Verification Time and Improving Reliability of Embedded System Hardware

In this whitepaper the author reviews how leveraging VTOS during the prototype phase can assist engineers in overcoming the challenges design complexity exerts on product development, manufacturing, and overall time-to-market. Readers will gain insight into how they can replace today’s ad-hoc board level verification approaches with an ordered methodology that enables designers to automatically validate their own hardware designs, optimize system performance, and simplify the process of integrating new hardware with new software.


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