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Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Accelerating Your Analog Output Design

Eventually, most of our designs need to control something in the real world. That means we have to bust out of our safe little digital realm, and drive some analog actuators or something similar. But, building that analog output section from scratch can be a real challenge. In this episode of Chalk Talk, Amelia Dalton talks to Bill Laumeister of Maxim Integrated about the Analog Output Design Accelerator Kit (MAXREFDES24EVSYS), a complete platform for easy evaluation that requires no lab equipment.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Achieve DDR3 Signoff With Power-Aware Timing Analysis

Cadence and EMA have collaborated to provide a unique power-aware DDR timing sign off flow for complete cycle-accurate system level simulation and analysis. You can now sign off on your entire DDR interface with total confidence.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Library Creation Solutions

As designs become more complex, it's important to identify opportunities to enhance design processes. Designers need an efficient way to create accurate, complex, schematic symbols and PCB footprints. EMA Design Automation has a solution to fill that need with an automated, efficient, process for creating component symbol and footprint data.

chalk talks

Vault-Driven Electronics Design

In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how to set up a robust design-for-re-use design methodology for your team that will flow nicely with your project, won’t take much effort to set up, and will bring BIG TIME long-term benefits of design re-use, configuration management, and manufacturing handoff.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

Integrated Design Environment for FPGA

Do you find that FPGA design flows can get a bit confusing and difficult to manage? What we really need is an integrated design environment that will help us keep our design activities organized. In this episode of Chalk TalkHD Amelia chats with Satyam Jani from Aldec about integrated design environments (IDEs) for FPGA design, why FPGA designers need a vendor-independent IDE, and how an FPGA-centric IDE can help us get through our design flow quite a bit more easily.

Why Do I Need a Customizable ARM-based SoC?

In this episode of Chalk TalkHD Amelia chats with Todd Koelling of Altera about what’s inside these new SoC FPGAs and how you can get started designing with them.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

latest papers and content

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

SDSoC Development Environment: Estimation & Implementation

Part 1 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews the challenges in implementing a system in a Zynq® SoC device and how SDSoC helps resolve those challenges. Then the video shows a demo of SDSoC on an example design to generate performance estimate and run a full design implementation using those estimates, and verifying the results achieved on the evaluation board.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

SDSoc Development Environment Backgrounder

This backgrounder describes the features and benefits of the SDSoC™ Development Environment. The SDSoC development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use an Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

Introducing the SDSoC Development Environment

The SDSoC™ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

UltraScale + 16nm Technology and Portfolio Backgrounder

Learn about new memory, 3D-on-3D, and multi-processing SoC (MPSoC) technologies introduced in Xilinx’s new 16nm UltraScale+™ portfolio of FPGAs, 3D ICs and MPSoCs, collectively delivering a generation ahead of value for next generation systems. This backgrounder describes the innovations introduced in the Kintex®, Virtex®, and Zynq® UltraScale+ families and how they address a broad broad range of next generation applications, including LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT) applications.

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more on demand

SDNet Demonstration

Demonstration of a 'hitless' update in a 100Gbps per second programmable packet processing system using SDNet.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

Using Vivado with Xilinx Evaluation Boards

Learn how the board-aware features of the Vivado® Design suite can be used to quickly configure and implement designs targeting Xilinx Evaluation Boards. See how the IP Integrator presents all of the possible IP interfaces into the Board and how they can easily be configured and connected in your design. See how all of the logical and physical parameters and constraints are automatically assigned and passed to the downstream implementation tools.

From Simulation to Emulation – A Fully Reusable UVM Framework

This paper introduces an acceleration-ready UVM framework and explains why it is needed and how to create it. Readers will learn how to write block-level UVM environments that can be reused directly in emulation for block, subsystem, and system level verification. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Spartan-6 FPGAs in Video Designs

In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.

Linking Early Mechatronic System Analysis to Physical Testing

Comprehensive testing is critical for many systems; however, system design and test development are often at opposite ends of a project’s schedule. Benefits accrue in improved system quality and on-time delivery when design and test are pursued concurrently.  Recent advances in modeling, simulation, and test technology provide the ability to link system design to system test well in advance of prototype availability. This paper describes the technologies required to improve test quality and reduce development cycles.

All Programmable Abstractions Video

New All Programmable Abstractions initiative improves productivity of hardware designers and empowers systems and software developers to directly leverage Xilinx All Programmable devices.

Optimizing Performance, Power, and Area in SoC Designs Using MIPS® Multi-threaded Processors

Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s. This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies’ multi-threading architecture and product offerings. The article also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the broad applicability of multi-threading in real-world applications.

Xilinx at NAB 2014 | OmniTek Ultra 4K Tool Box

David Ackroyd, Business Development Director for OmniTek demonstrates an an Ultra 4K Tool Box that includes conversions from 4K to/from SD including quad 3G-SDI.

Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!

What’s New in OrCAD PCB Editor 16.6

In this webcast Rocco Calvello, demonstrates the new features in version 16.6 of OrCAD PCB Editor. Rocco covers four major areas: operating system support, productivity enhancements, route interconnect optimization, DFM, and database & interface enhancements. Many of the productivity enhancements Rocco explains also have short demos so you can see them in action.

Choice of an ISA for Embedded Designs

Software investment is the biggest ticket item in any project. Hence the choice of an ISA that offers a scalable solution is an important consideration. MIPS and our SoC eco system offer distinct families of processor cores that span from 32-bit micro controllers all the way to 64-bit multi-threaded super-scalar cores from single-core to many cores, to address various segments of the embedded markets. For either a new design or a follow on or upgrade to an existing design, the choice of MIPS as the ISA offers an ideal path for protecting the software investment on a project, since one can scale the application up and down the performance scale seamlessly between a wide range of processors. The bulk of the effort in the migration to any new ISA is in the low-level initialization software. This paper illustrates the ease of migration from the ARM to MIPS architecture and highlight the areas that users need to focus on.

Introducing Xilinx Ultrascale™ Architecture: Industry’s First ASIC-Class All Programmable Architecture

The UltraScale™ Architecture addresses these challenges by applying leading-edge ASIC techniques in a fully programmable architecture. This architecture scales from 20nm planar through 16nm FinFET technologies and beyond, while also scaling from monolithic through 3D ICs. The UltraScale architecture not only addresses the limitations to scalability of total system throughput and latency, but directly addresses interconnect - the number one bottleneck to system performance at advanced nodes.

Addressing Design Challenges in Heterogeneous Multicore Embedded Systems

Heterogeneous multicore systems [architectures that combine two or more different types of microprocessors (MPUs) and microcontrollers (MCUs)] are quickly becoming the defacto architecture in the embedded industry today. The quick emergence of these systems can be attributed to a number of factors.

Integrated Power and System Management

In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.


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