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Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Productivity Enhancements in OrCAD PCB Editor

This short video provides a compilation of recent productivity improvements added to OrCAD PCB Editor such as 3D Viewing, Multi Trace Routing, Arc Editing, and more.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

How to Automatically Replace LEF Abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

How to Waive DRC Results Using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

chalk talks

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit

In this episode of Chalk TalkHD Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Timing Closure in FPGA Designs Made Easy with PlanAhead

In this episode of Chalk TalkHD Amelia chats with Frederic Rivoallon of Xilinx and they attempt to unravel the mysteries of timing closure and reveal that yes, you can get timing closure right the first time in your next design.

latest papers and content

PCIe Controller Solution

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence's high-performance, low-latency controller solution for PCI Express (PCIe).

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Productivity Enhancements in OrCAD PCB Editor

This short video provides a compilation of recent productivity improvements added to OrCAD PCB Editor such as 3D Viewing, Multi Trace Routing, Arc Editing, and more.

Intelligent PDF Generation

Often times it is necessary to share design information with other project members or partners who may not have access to a schematic capture tool or who you don’t want to have access to your design database. Creating a PDF is a perfect solution for this matter. Learn about how this new free OrCAD app enables you to create intelligent searchable PDFs.

Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

How to Automatically Replace LEF Abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

How to Waive DRC Results Using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Multi-Board Electrical and Thermal Co-Simulation Using PowerDC

Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.

TimingDesigner: Complex Diagrams

This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.

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The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

How Nvidia Is Speeding Up Timing Closure of Advanced-Node Application Processors

Designed for applications including tablets, smartphones, gaming cards, and supercomputers, Nvidia's high-performance, advanced-node application processors have stringent power and performance requirements and complex clocking schemes. In this video, Santosh Navale, a physical design engineer at Nvidia, talks about how Cadence® Encounter® Digital Implementation System CCOpt technology has improved concurrent datapath and clock optimization, the timing closure process, and overall chip performance. With CCOpt technology, Nvidia has been able to meet its tough design goals.

Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP

PCI Express® (PCIe®) Gen2 performance is no longer a “high-end” (read expensive) standard to support. With the certification of the Altera® Cyclone® V FPGA family, PCIe Gen2x4, design engineers now have a low cost alternative for their PCIe Gen2 applications.

AXI4 Interconnect Paves the Way to Plug-and-Play IP

In the past decade, the size and complexity of many FPGA designs exceeds the time and resources available to most design teams, making the use and reuse of Intellectual Property (IP) imperative. However, integrating numerous IP blocks acquired from both internal and external sources can be a daunting challenge that often extends, rather than shortens, design time. As today's designs integrate increasing amounts of functionality, it is vital that designers have access to proven, up-to-date IP from reliable sources.

It’s Easy to Protect Your Embedded System from Theft

If you have invested years and millions of dollars in the design of an embedded system (and in the creation of the Intellectual Property, or IP, that goes along with the design) it can be of critical importance to protect that system from unauthorized duplication or theft. After all, it’s much easier to steal something as complex as a multi-million gate FPGA design than to create, debug, and test it. The protection of an embedded system that uses FPGAs, is particularly relevant since FPGAs have become the platforms of choice for innovation.

Design Control, Data and Comparison with PADS Archive Management

Do you spend too much time archiving your designs, and later searching through archives for just that one project? Are your engineering reviews disorganized? Does your archive management flow store all the project files that you use? Files like libraries, reports, CAM data, etc.., not just design data? Are you able to quickly search archives, and compare and cross-probe between the schematic and layout files, or redline and append mark-up notes?

Proper archives are essential to back up and manage design data. A design-driven storage methodology promotes effective data backups, increasing productivity by efficiently creating, indexing, and restoring archives within a vault.

“Smart” Connected Home Entertainment with Android

Experience the SmartCE (Connected Entertainment) for Android platform from MIPS Technologies in this new video demonstration. The SmartCE Platform enables MIPS licensees and their customers to bring differentiated connected entertainment solutions to market quickly.

FPGA Design Flow and Development Tools

Learn about the Actel tools that are available for creating your FPGA design, whether it be for the ultra low power IGLOO®, high performance ProASIC®3, mixed signal Fusion, or Actel's new SmartFusion™ intelligent mixed signal flash FPGA with hard embedded ARM® Cortex™-M3 microcontroller subsystem.

CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS

In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC discusses an aggressive RF design with distortion problems in the lab, and how a solution was developed in collaboration with Cadence® FAEs using Cadence Spectre® Accelerated Parallel Simulator's distortion summary feature. This solution provided improved visibility into circuit operation to speed up the distortion-sensitive design cycle by 30%, and more deterministic silicon performance leading to fewer disconnects between simulation and lab. Learn more about the Spectre Accelerated Parallel Simulator at http://bit.ly/1tUYTQ1.

EWIS Requirements: The Business Challenge

Without proper planning and the evolution of their business to efficiently deal with the EWIS mandates, companies could find themselves in a very costly situation. This paper investigates the issues surrounding EWIS compliance and methods to minimize both cost and potential program delays.

HDR-60 Overview

Watch the 5-minute HDR-60 Overview Video to: Understand the features and capabilities of the HDR-60 development kit, See the exceptional performance of the HDR-60 Video Camera Development Kit, Performing Fast Auto Exposure that quickly adjusts to changing light, Delivering greater than 120dB High Dynamic Range (HDR) Performing high quality Auto White Balance

UltraFast™ Design Methodology Guide for the Vivado Design Suite

This Guide discusses a design methodology process to follow in order to achieve an efficient and quicker design implementation, and to derive the maximum value from Xilinx devices and tools.

Industry's First 28-nm High-End FPGA Running at 14.1 Gbps

Get an initial look at the industry’s first 28-nm high-end FPGA. In our Stratix® V FPGAs, you’ll get devices featuring: An industry-record 3.9 billion transistors, One million logic elements, Integrated transceivers with data rates up to 28 Gbps and an abundance of hard intellectual property (IP) blocks. Samples are shipping now. Watch this 3-minute video to see the progress of our silicon checkout process, as well as 14.1-Gbps transceiver performance.

Video Processing on FPGAs for Military Electro-Optical/Infrared Applications

This white paper explores Altera’s low-power FPGA platform and the video design solutions that address the military’s complex, power-budget-constrained EO/IR design challenges and significantly increase designer productivity. Many of today’s electro-optical/infrared (EO/IR) systems require high-complexity, real-time video processing within a constrained power budget. The latest low-power, low-cost FPGA families are ideal for developing the next generation displa and EO/IR systems.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Seven Steps to an Accurate Worst-Case Power Analysis Using Xilinx Power Estimator (XPE)

Power and cooling specifications for an FPGA design have to be determined early in the product’s design cycle, often even before the logic within the FPGA has been designed. An accurate worst-case power analysis early on helps you avoid the pitfalls of overdesigning or underdesigning your product’s power or cooling system

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.


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