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Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

The Rise of Serial Memory and the Future of DDR

With no plans emerging to define a "DDR5" specification, the entire memory landscape is going to change over the coming years. Serial memory technologies like Hybrid Memory Cube (HMC) and other schemes still in the pipeline can be expected to fill the memory needs of the future. From the beginning, Xilinx has engineered its UltraScale™ devices and platforms with the future in mind, providing a seamless transition to these newly emerging serial memory technologies.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance. Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applications

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

chalk talks

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

Design @ MachXO2 Speed

Just about every design needs one - that magic, do-anything part that can connect nearly any two things together and can aggregate all those messy, left-over functions on our board. Today's low density PLDs have remarkable capabilities at a tiny cost and power budget. In this episode of Chalk Talk HD Amelia Dalton chats with Steve Hossner (Lattice Semiconductor) about the amazing capabilities of Lattice’s latest low density PLD line, the MachXO2.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

latest papers and content

The Rise of Serial Memory and the Future of DDR

With no plans emerging to define a "DDR5" specification, the entire memory landscape is going to change over the coming years. Serial memory technologies like Hybrid Memory Cube (HMC) and other schemes still in the pipeline can be expected to fill the memory needs of the future. From the beginning, Xilinx has engineered its UltraScale™ devices and platforms with the future in mind, providing a seamless transition to these newly emerging serial memory technologies.

The Application of FPGAs for Wireless Base-Station Connectivity

This white paper addresses the application of Xilinx FPGA technology to the implementation of internal communication networks within wireless base stations. This is a critical element of the system design within a range of base-station architectures, including conventional macrocell, high-density cell sites, CRAN configurations, and AAA configurations.

Library Creation Solutions

As designs become more complex, it's important to identify opportunities to enhance design processes. Designers need an efficient way to create accurate, complex, schematic symbols and PCB footprints. EMA Design Automation has a solution to fill that need with an automated, efficient, process for creating component symbol and footprint data.

What’s New in PSpice 16.6

In this webcast Matthew Harms demonstrates the new features in version 16.6 of Cadence PSpice. Matthew covers three major areas: productivity enhancements, core enhancements, and TCL Integration. This webcast covers most of these features with an explanation and a short demonstration.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs

This Virtex® UltraScale™ FPGA demonstration shows the newly integrated Interlaken IP core running at 150Gb/s over 12 lanes. By integrating Interlaken, Xilinx is able to reduce power consumption, logic utilization, and design complexity for one of the most popular protocols in networking today.

Virtex UltraScale VU440 FPGA Demonstration

See the new Virtex® UltraScale™ VU440, the world’s largest FPGA, in action being used to prototype 10 ARM® Cortex®-A9 CPUs.

Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applications

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.

New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance. Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

What’s New in Capture 16.6

OrCAD 16.6 is here. Watch this free webcast to learn what's new in the latest release of OrCAD Capture, including enhancements in productivity, usability, and features. Highlights: • Database Enhancements • CIS Explorer Improvements & Customization • Tcl Expansion • SI Integration • Improved Symbol Creation

PSpice Modeling

Join EMA for an on-demand webinar to learn more about part modeling in Cadence® PSpice®, the industry’s #1 analog simulator. We will highlight features such as creating parts from a datasheet, using vendor supplied models, and modifying existing parts.

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more on demand

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Advanced Timing Exception Multicycle Path Constraints

Learn Xilinx recommendations for constraining multicycle path constraints. Understand and apply multicycle path exception constraints in your design.

Wireless Base Station ZUC Block Cipher Implementation on Zynq SoCs

The Xilinx Zynq®-7000 All Programmable SoC provides a flexible platform that offers programmability for evolving technologies like LTE and new standards including, but not limited to, the ZUC algorithm. This white paper illustrates the advantages of the Zynq SoC-based design methodology using the Vivado® Design Suite, which facilitates an optimal hardware/software partitioning of the system functionality for better performance.

Effective Version Control for Electronic Design

When it comes to our hardware engineering projects, we need to keep our design data well organized. In the software world, this is accomplished with the help of version control systems. Unfortunately, most of us don’t learn version control for hardware design. In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how effective version control can help every step of the design process, enable team design, manage versions and configurations, and keep our project from spiraling out of control.

System-Level Debugging and Monitoring of FPGA Designs

This white paper describes the latest state-of-the-art methods for debugging and monitoring large FPGA designs both during the simulation phase of development and after device configuration, and details the current practices that Altera has identified across a representative number of customer designs.

SystemVision® Versatile System Modeling Datasheet

SystemVision models circuits to systems in a single, easy-to-use analysis environment. Build systems and circuits using models from SystemVision’s large VHDL-AMS and SPICE model libraries. Model component tolerance, distribution, and stress details to improve system performance and reliability. Build and share libraries of custom simulation models.

Video Processing on FPGAs for Military Electro-Optical/Infrared Applications

This white paper explores Altera’s low-power FPGA platform and the video design solutions that address the military’s complex, power-budget-constrained EO/IR design challenges and significantly increase designer productivity. Many of today’s electro-optical/infrared (EO/IR) systems require high-complexity, real-time video processing within a constrained power budget. The latest low-power, low-cost FPGA families are ideal for developing the next generation displa and EO/IR systems.

Motor Efficiency Depends Upon Power Factor

Electric motor efficiency is taking center stage these days not only because the potential power savings are significant, but also because the technology for achieving them is now available. This white paper discusses the factors that are critical in achieving overall system power savings, taking into consideration the rectifier that conditions input power from the AC mains and the variable frequency inverter drive electronics of the motor. Active power factor correction for the rectifier used in modern motor drives is required to keep the generated line harmonics within regulatory limits and reduce wasted power. Mixed-signal FPGAs, by doing many calculations in parallel, can perform better than other possible motor control and power factor correction implementations.

Accelerating DSP Designs with the Total 28-nm DSP Portfolio

Implementing DSP datapaths with different performance, precision, IP, and development flows is challenging and labor intensive. As more and more high-performance DSP datapaths are implemented on FPGAs, Altera has developed a complete DSP solutions portfolio at 28 nm to address these challenges and speed up the design cycle for FPGA-based applications. This white paper discusses the different components of this portfolio and how they come together to accelerate the implementation of a DSP design.

Setting and Editing Device Properties in Vivado

Learn how to use the new configuration dialog to set and edit device properties. Understand and utilize the configuration dialog for setting and editing device properties.

The Importance of IP at STMicroelectronics

Peter Hirt, IP Procurement & IP Partnership Manager at STMicroelectronics, details the role of IP in advanced node designs, IP provider requirements and Cadence's comprehensive IP portfolio.

EDS Design Tools for Electric Vehicles

This paper explores how challenges for electric vehicles from battery placement to electrical distribution to eliminating crosstalk between high- and low-level signals can be solved with advanced EDS software. Also see how design environments incorporate features for designer to address product plans and answer tomorrow's demand for fully electric vehicles.

How to Effectively Manage Timing of FPGA Design Flow

When combined with advances in FPGA technologies for interface design efforts, EMA TimingDesigner can simplify design issues and provide advanced accurate control of virtually any interface. From simple SRAM interface protocols to high-speed source synchronous interface protocols, TimingDesigner allows designers to identify potential timing problems early in the design process and thereby providing the greatest opportunity to get the timing right the first time. This white paper will show you how to effectively integrate TimingDesigner with Xilinx and Altera Development Systems.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

Multiplying the Value of 20nm with UltraScale Devices: Doing More for Less

Xilinx is multiplying the value of 20nm with the UltraScale™ architecture and associated family of FPGAs and 3D ICs. Whether viewed from almost every attribute at the chip level or viewed when integrating multiple chips into one or fewer chips at the system level, you will find compelling value metrics as you migrate to an UltraScale solution. UltraScale architecture and Vivado® Design Suite are co-optimized to enable a device utilization target of 90%, which can result in up to a 30% effective cost advantage for the next generation of smarter, high performance systems in: Packet processing: Multi-hundred gigabit throughput Waveform processing: Multi-teraMAC throughput Image and video processing: 8K4K image and video processing and transport High performance computing: Multi-teraflop throughput Learn More about potential chip and system level value multipliers.

Microchip's Accessory Framework for Android(tm)

The Microchip's Accessory Framework for Android provides a mechanism to transfer data to and from an Android application through the USB of the microcontroller.

Seven Steps to an Accurate Worst-Case Power Analysis Using Xilinx Power Estimator (XPE)

Power and cooling specifications for an FPGA design have to be determined early in the product’s design cycle, often even before the logic within the FPGA has been designed. An accurate worst-case power analysis early on helps you avoid the pitfalls of overdesigning or underdesigning your product’s power or cooling system


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