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Strategies to Develop Secure and Robust Embedded Devices

Learn a pragmatic approach to configuring a heterogeneous multicore ARM® device built with ARM TrustZone™ technology and trade-offs of various implementations.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

World's Smallest FPGAs Solve 4 Big Problems

In this episode of Chalk Talk, Amelia chats with Gordon Hands (Lattice Semiconductor) about some awesomely tiny FPGAs that bring the power of programmable logic into devices like cell phones, tablets, and other power and form factor sensitive applications.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Injecting Automation into Verification - Assertions

What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays video, Moshik Rubin discusses the history of the PCI Express standard. Moshik starts with PCIe Gen1, which originated in 2002, and walks through the doubling of throughput offered by each new generation, ending with PCIe Gen4.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

It’s Easy to Protect Your Embedded System from Theft

If you have invested years and millions of dollars in the design of an embedded system (and in the creation of the Intellectual Property, or IP, that goes along with the design) it can be of critical importance to protect that system from unauthorized duplication or theft. After all, it’s much easier to steal something as complex as a multi-million gate FPGA design than to create, debug, and test it. The protection of an embedded system that uses FPGAs, is particularly relevant since FPGAs have become the platforms of choice for innovation.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

15Gb/s HMC Interface for UltraScale Devices

Watch a demonstration of the industry's first 15Gb/s HMC interface by Xilinx and Pico Computing at the International Supercomputing Conference.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

System Design with Advance FPGA Timing Models

Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

chalk talks

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Integrated Power and System Management

In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

High Speed Data Acquisition and Software Defined Radio Made Simple

Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk TalkHD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Why Do I Need a Customizable ARM-based SoC?

In this episode of Chalk TalkHD Amelia chats with Todd Koelling of Altera about what’s inside these new SoC FPGAs and how you can get started designing with them.

latest papers and content

Injecting Automation into Verification - Assertions

What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

Strategies to Develop Secure and Robust Embedded Devices

Learn a pragmatic approach to configuring a heterogeneous multicore ARM® device built with ARM TrustZone™ technology and trade-offs of various implementations.

Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesday video, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

15Gb/s HMC Interface for UltraScale Devices

Watch a demonstration of the industry's first 15Gb/s HMC interface by Xilinx and Pico Computing at the International Supercomputing Conference.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays video, Moshik Rubin discusses the history of the PCI Express standard. Moshik starts with PCIe Gen1, which originated in 2002, and walks through the doubling of throughput offered by each new generation, ending with PCIe Gen4.

Selecting an Operating System (OS) for Embedded Application

It seems these days, just about every embedded system has some type of operating system. And there are more options today as to which OS to choose. Is open source your best choice? What about a free RTOS? In this paper, learn the pros and cons of the many OS options available today and how to select the right OS for your next embedded project.

Navigating the FDA Approval Process for Your Software Based Medical Device

Understand how to get your product to market within product launch schedules. Review challenges companies face as they seek FDA approval and review guidance and resources to assist with successfully navigating the approval process. Learn about a number of important areas including premarket submissions, documentation, verification and validation (V&V), user experience and human factors design, and cybersecurity.  Presented by Steve Robertson with Mentor Graphics Embedded Software.  

Using USB IP Controllers in Today's Devices

In this week's Whiteboard Wednesdays video, Jacek Duda follows up on his earlier video focused on USB performance and now takes a closer look at USB IP controllers and their roles in today's devices.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

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LatticeECP3 Family

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

7 Series FPGA Transceiver RX Margin Analysis

Many designers either don’t have the equipment to debug an FPGA serial link or when they do, they don’t get much information by physically probing traces on the board. Using PCI-Express as an example, this demonstration will show how to perform system margin analysis during live signal transmission without interrupting data flow.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Accelerating SoC FPGA Design in Complex Systems

The SoC FPGA design is a new device that incorporates both FPGA and microcontroller subsystem on a single device. As these devices capabilities extend to high speed serial and DDR memory interfaces, and high performance FPGA fabric with DSP processing, the architecture within the device requires an advanced tool methodology to simplify the designer’s experience and accelerate time-to-market. System Builder accomplishes this by guiding users visually, presenting a high level abstraction for construction and then generating a “correct by construction” implementation of the system components.

Secure Foundations

In a world where attacks on electronic systems can be conducted remotely, security is a vital component of system design. Even systems that do not have to store personal or commercially confidential data now have to be designed with security in mind to prevent their core intellectual property (IP) from being copied and reused illegally. In these examples, we can see the two elements of electronic system security: design security and data security. Increasingly, the two depend on each other.

Optimize Your 28-nm FPGA Design for Maximum Performance

Want the best performance from your 28-nm FPGA design? Find out how you can make optimal use of Altera's 28-nm architecture to maximize your system performance. Watch this 10-minute webcast to learn about: Our 28-nm architecture innovations, Recommended design optimization techniques and Quartus® II software automated optimization tool.

Overcome Design Challenges with an Innovative IP Scalability, Integration, and Delivery Model

Intellectual property (IP) is a key component in system designs for many different end markets. This white paper explores how Altera and partner IP solutions can provide the differentiation you need for your next-generation applications. This white paper examines the feasibility of developing IP in-house or buying from a third party, and also presents Altera's innovative IP scalability, integration, and delivery model. With this model, Altera not only simplifies the process of acquiring, evaluating, testing, and integrating IP into your design, but also mitigates the risks of using third-party IP.

Implementation of 9x9 Multiplications, Wide-Multiplier, and Extended Addition Using IGLOO2/SmartFustion2 Mathblock App Note

This application note highlights design guidelines and different implementation methods to achieve better performance results while implementing wide-multipliers, 9-bit×9-bit multiplications, and extended addition with the IGLOO2/SmartFusion2 mathblock (MACC). The 9-bit×9-bit multiplications, wide-multiplier, and extended addition are ideal for applications with high-performance and computationally intensive signal processing operations. Some of them are finite impulse response (FIR) filtering, fast fourier transforms (FFTs), and digital up/down conversion.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Design @ MachXO2 Speed

Just about every design needs one - that magic, do-anything part that can connect nearly any two things together and can aggregate all those messy, left-over functions on our board. Today's low density PLDs have remarkable capabilities at a tiny cost and power budget. In this episode of Chalk Talk HD Amelia Dalton chats with Steve Hossner (Lattice Semiconductor) about the amazing capabilities of Lattice’s latest low density PLD line, the MachXO2.

Vault-driven Electronics Design Whitepaper

The ‘endgame’ for any board design is to generate and manage data from that design for building the physical object captured by that design – and with the utmost integrity. However, the need to ensure high-integrity data often walks hand-in-hand with layers of bureaucratic ‘red tape’, resulting in the designer being confined to design according to formalized processes, locking down design changes to ensure minimal impact to the integrity of the design data.

Extending the Spartan-6 FPGA Connectivity TRD (PCIe-DMA-DDR3-GbE) to Support the Aurora 8B/10B Serial Protocol

Targeted Reference Designs (TRDs) provide Xilinx designers with turn-key platforms to create FPGA based solutions in a wide variety of industries. This application note extends the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD to support Aurora 8B/10B serial protocol.

Xilinx and Huawei Discuss 400GE Networking

In this live presentation at OFC 2014, Huawei and Xilinx discuss how they are working together to solve the challenges associated with 400GE network readiness. This presentation also discusses the key technologies in 400GE and how programmable technology is playing a key role to expedite the development and deployment of Huawei's future IP router products in the networking infrastructure.

Embedded Signal Processing Capabilities of the LatticeECP3 sysDSP Block

To address these emerging needs, Lattice Semiconductor has continued its tradition of providing high performance DSP capabilities in its most recent low-cost, SERDES-capable LatticeECP3 FPGA family. Features such as a dual slice architecture, the ability to cascade/chain DSP slices and blocks and an enhanced instruction set establish the LatticeECP3 family as a compelling alternative for signal processing applications such as FIR filtering and FFT/iFFT implementations.

Battle Board Demo: Virtex-7 FPGA GTH Transceiver vs. Altera Stratix V GX Transceiver

As designers clamor for 10G+ chip-to-chip and backplane performance, they rely on receiver equalization to compensate for signal distortion. Watch this side-by-side comparison of equalization capabilities of the Xilinx® Virtex®-7 FPGA GTH transceiver vs. the Altera Stratix V GX transceiver.

Practical Use of FPGAs and IP in DO-254 Compliant Systems

How can a designer use commercially available IP within a DO-254 compliant system?

Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors

Single event effects (SEEs) are of a growing concern in high-reliability system development, yet there is much disparity among users of ASICs and FPGAs with regard to understanding how susceptible their designs might be.

First Virtex UltraScale FPGA Demonstration

Watch a demonstration of the first device in the industry's only 20nm high end family—the Virtex® UltraScale™ VU095 device—featuring GTY transceivers capable of 32.75G short reach and 28.21G backplane operation, ideal for implementing next generation 400G and 500G wired networking systems.


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