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Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

Troy Scott, Product Marketing Manager, and Peter Zhang, R&D Engineer, explain RTL debug features available in ProtoCompiler.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

chalk talks

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Verification Methodologies (Made Easy)

Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

latest papers and content

SDAccel Development Environment Demonstration

This video demonstrates the SDAccel™ development environment for acceleration using a standard X86_64 workstation containing an Alpha data ADM-PCIE-7V3 accelerator.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors fabric behavior, and the Interconnect Workbench for performance analysis. The combined solution delivers functional verification along with latency and bandwidth analysis to fine-tune interconnect performance.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effecitvely, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

OrCAD Now – PSpice

This presentation is on the benefits of using PSpice® in an integrated OrCAD flow. For new users, it covers how to get started and where to find working examples. The next step is where to find specific models and how to create them if they’re not available anywhere. Finally it will go deeper into the tool to see how it can help us if we run into trouble by identifying parts that are close to failure.

Xilinx Product Teardown at ARM Tech Con: What's In There Besides Zynq SoCs?

Watch Steve Leibson, Editor of the Xilinx Xcell Daily Blog, moderate two product tear downs featuring the National Instruments Virtual Bench and the Cloudium Integrated Media Processing Platform.

Xilinx at ARM TechCon 2014: Booth demonstration presented by National Instruments

Eric Myers, Product Manager for Embedded Products, National Instruments, demonstrates the Airbus Smart Tools concept for their Factory of the Future using the NI System on Module (SOM).

TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification.

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Using Low Cost, Non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Achieving 25 Gbps Transceiver Performance on 28nm FPGAs

Need high bandwidth for your next-generation design? Watch our 9-minute video to see 25-Gbps transceiver performance on a 28nm device. You will: See a live demo of our 28nm transceiver technology running a pseudo-random bit pattern at 25 Gbps, See transmit and receive eye diagrams across a 10GBASE-KR backplane running at 10 Gbps, Learn more about our 28nm Stratix® V FPGAs, which feature integrated 28-Gbps transceivers.

SmartFusion2 FPGAs: Breakthrough Capabilities for Advanced Security, High Reliability and Low Power FPGA Applications

Microsemi has created the new SmartFusion®2 family of system-on-chip (SoC) field programmable gate arrays (FPGAs), which directly address these challenges and deliver the advanced security, high reliability and low power capabilities that this growing class of mission critical applications demands. Additionally, Microsemi believes that these requirements are no longer relegated to a narrow class of applications, but span a majority of the deeply interconnected electronics systems being designed today. This white paper will illustrate how the Microsemi SmartFusion2 family holds the promise of creating a much more secure and reliable future for all of us.

Selecting an Operating System (OS) for Embedded Application

It seems these days, just about every embedded system has some type of operating system. And there are more options today as to which OS to choose. Is open source your best choice? What about a free RTOS? In this paper, learn the pros and cons of the many OS options available today and how to select the right OS for your next embedded project.

Tackling Verification Challenges with Interconnect Validation Tool

As the capacity of today’s SoCs continues to increase dramatically, interconnect verification complexity also grows, considering the master/slave numbers, various protocols, different kinds of transactions, and multi-layered topology. The traditional ways of firing many direct tests, or applying a divide-and-conquer strategy, do not provide a holistic verification for SoC interconnects. A systematic approach must be adopted to tackle the challenge and make the process more efficient.

Using LEDs as Light-Level Sensors and Emitters

Modulating LED power based on ambient light level increases battery life, a particularly helpful feature in a device where battery life is measured in days. Using a very simple circuit, Altera’s MAX II and MAX IIZ CPLDs can measure the analog light level of their environments and then drive an LED at a proportional analog intensity level. Controlling the LED intensity based on ambient light as demonstrated reduces LED energy usage by more than 47 percent without affecting appearance.

Smarter Networks Backgrounder

Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. But just what do those words mean? It means that the FPGA fabric, the fundamental building block of all Xilinx silicon products—All Programmable FPGAs, 3D ICs, and SoCs—has reached a critical threshold at the 28nm process node. This threshold marks the transition where FPGAs have evolved to the point where they are large enough and fast enough to implement complete systems. At 28nm, Xilinx is capable of replacing entire ASSPs and ASICs, which means that a Xilinx All Programmable device equipped with the right IP and software may well be the only significant integrated circuit needed to implement many end products. Read the incontrovertible proof in this backgrounder.

A Methodology to Manage Mechatronic Development in Medical Electronic Products

Model Driven Development (MDD) dramatically reduces the risks of complex mechatronic system development, increases productivity within an FDA-regulated process, and automates collaborative development among disparate teams. An MDD flow gives the system integrator an effective platform from which to communicate the overall system requirements and can also tie project management into development and automate mundane/time-consuming tasks, so designers can spend their time doing what they do best – designing.

Introducing the Avnet TI OMAP/Spartan-6 FPGA Co-Processing Kit

FPGA-based co-processing is 15X faster than traditional processor/DSP systems. Conventional system design methods face stiff challenges to meet the requirements of today’s ultra-high performance applications. This video explains how the TI OMAP/Spartan-6 FPGA Co-Processing Kit delivers breakthrough system performance by integrating and optimizing the key strengths of high performance FPGAs, system control processing, and digital signal processing, all within one single environment.

Meeting the Performance and Power Imperative of the Zettabyte Era with Generation

Today’s Information and Communications Technology (ICT) equipment developers face a daunting problem in addressing exponential growth in bandwidth demand while minimizing power consumption. This white paper outlines the performance and power requirements for next-generation programmable logic solutions to meet the demands of the growing ICT sector by leveraging multiple process technologies and revolutionary approaches to transistor design, new architectures, and comprehensive device-level power features.

High Performance Computing Using FPGAs

For over a quarter of a century, Xilinx® FPGAs continue to be the platform of choice for designing programmable systems. Due to their inherent flexibility, Xilinx FPGAs have been used in programmable solutions such as serving as a prototype vehicle as well as being a highly flexible alternative to application-specific integrated circuits. This white paper describes the various use models for applying FPGAs in High Performance Computing (HPC) systems.

Optimizing and Maintaining a High-Performing Design Environment

To maximize your investment in EDA tools, your infrastructure and processes must be optimized for growing and frequently changing design needs. Cadence Client Technology Solutions is dedicated to enhancing EDA tool performance, ensuring stability, and removing critical bottlenecks. Through close collaboration with hundreds of customers worldwide, we have unique insight into environmental conditions and how best to maintain a high-performing design environment.

Using Vivado with Xilinx Evaluation Boards

Learn how the board-aware features of the Vivado® Design suite can be used to quickly configure and implement designs targeting Xilinx Evaluation Boards. See how the IP Integrator presents all of the possible IP interfaces into the Board and how they can easily be configured and connected in your design. See how all of the logical and physical parameters and constraints are automatically assigned and passed to the downstream implementation tools.

SmartFusion2 Product Brochure

Microsemi's next-generation SmartFusion2 SoC FPGAs are the only devices that address fundamental requirements for advanced security, high reliability and low power in critical industrial, military, aviation, communications and medical applications. SmartFusion2 integrates an inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM® Cortex™-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM, and industry-required high-performance communication interfaces all on a single chip.

Xilinx 4x100G Transponder Reference Design

Learn about Xilinx's 4x100G Transponder Reference Design running on the VC730 OTN Test Development Platform.

Automating DSP Simulation and Implementation of Military Sensor Systems

Military sensor-driven systems normally use FPGAs to interface with the ADCs that digitize sensor inputs. Because ADCs operate at rates of up to 3 MSPS, they require very high-performance DSP circuitry. In most cases, this functionality is implemented using FPGAs optimized for DSP applications.

Two Reasons Why Auto-Adaptive Equalization is Critical to Transceiver Design

Systems with high speed serial links often have serial channels which result in signal distortion described as insertion loss, reflection, cross-talk, and other channel impairments. Receiver equalization can help compensate for such channel-driven losses and distortions, but link tuning and bring-up can be non-trivial even for the most experienced transceiver and signal integrity specialists. Learn how Xilinx FPGAs with fully auto-adaptive equalization is critical to high speed transceiver design and enables system designers to get their systems up and running quickly.

IGLOO FPGA Product Brief

IGLOO®2 FPGAs integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and math blocks for digital signal processing (DSP)and much, much more.


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