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Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

The Great Divide: Why Next-Generation FPGA Designs will be Hierarchical and Team-Based

This paper first considers the evolution of FPGAs and FPGA design. Next, the concepts of top-down and divide-and-conquer design flows are introduced. Also discussed are considerations and capabilities required to support true hierarchical team-based design along with content management and design reuse considerations.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

A Methodology to Manage Mechatronic Development in Medical Electronic Products

Model Driven Development (MDD) dramatically reduces the risks of complex mechatronic system development, increases productivity within an FDA-regulated process, and automates collaborative development among disparate teams. An MDD flow gives the system integrator an effective platform from which to communicate the overall system requirements and can also tie project management into development and automate mundane/time-consuming tasks, so designers can spend their time doing what they do best – designing.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

chalk talks

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Simplifying Industrial Ethernet Design

In this episode of Chalk TalkHD Amelia chats with Suhel Dhanani of Altera about the who, what, and how of industrial ethernet design.

Introducing SmartFusion2 FPGAs

In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about Microsemi's biggest FPGA announcement this year - SmartFusion2. This new family can do things we never expected from Microsemi's non-volatile FPGAs. Watch this Chalk Talk to learn what it's all about.

Hardware/Software Co-Verification of ARM Processor-Based Designs

In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti of EvE about the latest in emulation technology and explains how you can use emulation to dramatically accelerate software development, which is becoming the most time-consuming part of SoC design.

Power Supply Management in High-Availability Systems

One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

latest papers and content

VeriSilicon and Cadence Customer Success Story

With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.

ASIC Prototyping Simplified

To use current solutions for application-specific integrated circuit (ASIC) prototyping using field-programmable gate arrays (FPGAs), you either have to create custom boards or buy off-the-shelf FPGA boards. Off-the-shelf boards don’t satisfy the requirements for complex systems on chips (SOCs), and they’re expensive and lack scalability. Cadence Allegro FPGA System Planner fills the gap, offering a simplified approach to ASIC prototyping.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

USB Controller Connectivity

In this week's Whiteboard Wednesday video, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC), and how they improve connectivity between multiple USB applications. Learn more about Cadence IP at http://ip.cadence.com.

A Methodology to Manage Mechatronic Development in Medical Electronic Products

Model Driven Development (MDD) dramatically reduces the risks of complex mechatronic system development, increases productivity within an FDA-regulated process, and automates collaborative development among disparate teams. An MDD flow gives the system integrator an effective platform from which to communicate the overall system requirements and can also tie project management into development and automate mundane/time-consuming tasks, so designers can spend their time doing what they do best – designing.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Faster Wiring and Harness Design

Does your electrical design software just do the basics? Or does it take the complexities of today's designs out of the task and save you time and money? This short white paper outlines the top ten highlights of how new tools make wiring and harness design faster and better.

EWIS Requirements: The Business Challenge

Without proper planning and the evolution of their business to efficiently deal with the EWIS mandates, companies could find themselves in a very costly situation. This paper investigates the issues surrounding EWIS compliance and methods to minimize both cost and potential program delays.

EDS Design Tools for Electric Vehicles

This paper explores how challenges for electric vehicles from battery placement to electrical distribution to eliminating crosstalk between high- and low-level signals can be solved with advanced EDS software. Also see how design environments incorporate features for designer to address product plans and answer tomorrow's demand for fully electric vehicles.

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True Wireless Broadband

Mark Quartermain of Xilinx explains how the next generation of 4G digital cellular standards, Long Term Evolution, represents a significant step forward for wireless operators...and more!

Xilinx and ARM Address New Markets

Ian Ferguson, VP of Segment Marketing at ARM, explains how an ARM processor combined with an FPGA addresses the embedded space. He also discusses three areas where programmable logic provides the most value along with the new markets addressed by the Zynq®-7000 All Programmable device.

Innovative Non-Volatile Configuration Memory Technology Enables Low-Cost Multi-Time Programmable ULD FPGAs

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

An Independent Analysis of Altera's FPGA Floating-Point DSP Design Flow

BDTI performed an independent analysis of Altera’s floating-point DSP design flow. BDTI’s objective was to assess the performance that can be obtained on Altera FPGAs for demanding floating-point DSP applications, and to evaluate the ease-of-use of Altera’s floating-point DSP design flow. This paper presents BDTI’s findings, along with background and methodology details.

Basics of Programmable Logic Online Training

This training will give you a basic introduction to programmable logic devices, focusing on FPGAs. By exploring the history of programmable logic technologies, you’ll learn about the architectural features that make up an FPGA. You will see the advantages of using FPGAs for digital logic design. Finally, you’ll understand how design software makes it easy to create and implement digital logic designs. By the end of this course, you will be able to describe the technologies that make up modern CPLDs and FPGAs, understand how programmable logic devices are programmed, understand the differences between CPLDs and FPGAs, and choose the right device technology for a design.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Automotive Top Ten - Ten Points to Consider When Using Logic in Your Next Automotive Design

Automotive electronics designers have been turning more frequently to programmable logic solutions to meet the needs of their next generation designs. FPGAs offer time-to-market benefits along with simplified qualification and greater flexibility in comparison to historic ASIC-based solutions. Actel is a leading supplier of FPGAs to the automotive industry. Actel parts are being used in the most demanding mission-critical systems, such as powertrain and safety subsystems, in addition to infotainment and body electronics designs.

No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs

Designers of FPGAs for military and aerospace applications need to increase the reliability and availability of their designs. This is particularly true in the case of mission-critical and safety-critical, high-reliability and high-availability FPGA design including: FPGA design and verification flows, methodologies, processes and standards, architectural and algorithmic exploration, geographically distributed design teams, IP selection and verification, DO-254 compliance and much more.

Optimizing Performance, Power, and Area in SoC Designs Using MIPS® Multi-threaded Processors

Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s. This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies’ multi-threading architecture and product offerings. The article also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the broad applicability of multi-threading in real-world applications.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!

MAX Series Configuration Controller Using Flash Memory

Altera’s flash memory configuration controller provides an alternative configuration solution for high-density FPGA-based designs. With the flexibility to use a bigger flash memory to store more configuration data, designers can implement the flash memory controller in MAX series devices for use in Stratix series, Arria series, and Cyclone series FPGAs. Configuration bitstream sizes are increasing with the higher-density FPGAs, which require larger devices to store and configure data.

Fast, Efficient RTL Debug for Programmable Logic Designs

In a typical FPGA design flow, most designers work from a written specification that contains architectural level drawings defining the major logic blocks, interfaces, and busses. The design manager begins to partition functionality based on the diagrams and to assign development based on the block’s functional descriptions. Each block is coded individually and may be simulated in a block-specific test bench. The team assembles the blocks into a device-level file where the ports are pins on the target device. The design is then ready to be compiled for simulation initiating the debug phase of development: Simulation followed by hardware debug.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

Mixed-Signal Power Manager (MPM)

Actel's Mixed-signal Power Manager (MPM) enables designers to control and reduce power at the system level, offering fully-verified, timing-closed, proven-in-hardware power supervision and management capabilities, while utilizing Actel Fusion mixed-signal FPGA. Watch the short webcast to learn more.

Verifying Your Designs with Simulation IP

In this week's Whiteboard Wednesdays installment, Tom Hackett takes a closer look at simulation verification IP (VIP), and how these IP cores help verify designs with protocol checks, test sequences, and other capabilities.

Put 1080p High-Definition Analytics into Your IP Camera

Advanced analytics is replacing simple motion detection in surveillance cameras. See how you can get 1080p high-definition (HD) analytics in your IP camera with a single-chip video analytics solution.

First Virtex UltraScale FPGA Demonstration

Watch a demonstration of the first device in the industry's only 20nm high end family—the Virtex® UltraScale™ VU095 device—featuring GTY transceivers capable of 32.75G short reach and 28.21G backplane operation, ideal for implementing next generation 400G and 500G wired networking systems.


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