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Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Sigrity PowerSI Tackles SSO Noise: Customer Success Story

AEI Systems needed to perform a worst case SSO analysis to screen their design and verify that defects and deficiencies would be eliminated prior to test, production and delivery. In doing so, they found that Cadence Sigrity PowerSI was the only tool tested that was able to provide the close correlation to the actual measurement needed to validate the RTAX board example. Click to see the process and results AEI Systems saw using Sigrity PowerSI to successfully evaluate worst case SSO noise.

i.MX 6SoloX – Freescale’s New Heterogeneous Multicore Applications Processor

Many applications today need both an applications processor AND a real-time MCU. But, most solutions don't offer both on the same chip. In this episode of Chalk Talk, Amelia Dalton chats with Amanda McGregor of Freescale about a new application processor that combines an ARM Cortex-A9 core with the efficiency and real-time capability of the Cortex-M4.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs

Xilinx discusses how programmable logic provides the partial reconfiguration capabilities, large number of high speed analog IOs and mix signal capabilities to build high density, scalable and flexible 500G/1T line cards today.

chalk talks

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

latest papers and content

Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs

Xilinx discusses how programmable logic provides the partial reconfiguration capabilities, large number of high speed analog IOs and mix signal capabilities to build high density, scalable and flexible 500G/1T line cards today.

Xilinx and Ixia present 400GE and 25GE testing solutions at OFC 2015

In this live presentation from OFC 2015, Xilinx talks with Ixia about how they surmounted the many obstacles to efficient 400GE and 25GE testing by leveraging Xilinx’s All Programmable devices to get the Ixia 400GE and 25GE tester families to market quickly. Presented by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.

i.MX 6SoloX – Freescale’s New Heterogeneous Multicore Applications Processor

Many applications today need both an applications processor AND a real-time MCU. But, most solutions don't offer both on the same chip. In this episode of Chalk Talk, Amelia Dalton chats with Amanda McGregor of Freescale about a new application processor that combines an ARM Cortex-A9 core with the efficiency and real-time capability of the Cortex-M4.

UltraScale Integrated 100G Ethernet IP for 10x10G and 4x25G

This video demonstrates how using an integrated Ethernet MAC can save power, integration time and logic utilization while delivering the highest possible flexibility. The UltraScale™ Integrated 100G Ethernet IP supports both CAUI-4 and CAUI-10 interfaces to CFP, CFP2, CFP4 and other pluggable optics. As shown in this video, the IP can easily and dynamically swap between interfaces.

Kintex UltraScale DSP Kit with 8 Lane JESD204B interface

The video highlights the Xilinx® Kintex® UltraScale™ FPGA Analog Devices JESD204B DSP Kit featuring the Xilinx Kintex UltraScale KCU105 development board with the KU40 device paired up with the Analog Devices AD-FMCDAQ2-EBZ high-speed analog FMC module. An 8 lane JESD204B interface is used to interface the data converters to the FPGA using GTX serial transceivers at the full 12.5 GSPS line rate. Xilinx devices are the world’s first to support the full JESD204B line rate across all device speed grades for mid-range JESD204B solutions, and the only all programmable solution available today at 20nm.

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

SDSoC Development Environment: Estimation & Implementation

Part 1 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews the challenges in implementing a system in a Zynq® SoC device and how SDSoC helps resolve those challenges. Then the video shows a demo of SDSoC on an example design to generate performance estimate and run a full design implementation using those estimates, and verifying the results achieved on the evaluation board.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

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Introducing Xilinx Ultrascale™ Architecture: Industry’s First ASIC-Class All Programmable Architecture

The UltraScale™ Architecture addresses these challenges by applying leading-edge ASIC techniques in a fully programmable architecture. This architecture scales from 20nm planar through 16nm FinFET technologies and beyond, while also scaling from monolithic through 3D ICs. The UltraScale architecture not only addresses the limitations to scalability of total system throughput and latency, but directly addresses interconnect - the number one bottleneck to system performance at advanced nodes.

Reducing Switching Power with Intelligent Clock Gating

The intelligent clock-gating optimization feature introduced in ISE Design Suite v12 greatly simplifies the effort to reduce dynamic power in FPGA designs. The traditional approach to clock-gating optimization used in ASIC design presupposes an intimate knowledge of the design, thereby virtually precluding optimization of legacy and third-party IP blocks. New tools, new steps, and complex timing analyses are typically required to compensate for the inevitable new “gated clocks” and the changes in logic that are produced.

Smart, Scalable Debugging with ZeBu

Modern SOC realization requires a development effort beyond that of traditional hardware verification. Creating a complete application-ready SOC platform now includes pre-tapeout software validation and hardware/software co-verification using full-chip RTL models. These billion-cycle scenarios are often beyond the scope of HDL simulation, but are ideal for emulation using EVE’s ZeBu hardware-assisted verification platforms.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Simulating Zynq BFM design using Synopsys VCS in Vivado

Learn how to run simulation with ZYNQ® BFM IPI design using Synopsys VCS simulator in Vivado®. We will provide a demonstration on how to compile simulation libraries, generate simulation scripts for an IP or an entire project and then run simulation.

Concept to X: Ten Steps to Effective Model Driven Development

Model Driven Development is proven to improve productivity in the design process. It makes it possible to use models all the way down the flow, automatically generating parts of the design and thus improving the design’s quality by bringing in repeatability and standards compliance. It enables actions such as eliminating physical prototypes from the process, by instead simulating digital and analog elements working together and with the control software operating the system.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

All Programmable Abstractions Video

New All Programmable Abstractions initiative improves productivity of hardware designers and empowers systems and software developers to directly leverage Xilinx All Programmable devices.

Beyond the Hype: MIPS® - the Processor for MCUs

A market leader in the Digital Home and Networking sectors, MIPS has adapted its industry-standard MIPS32® architecture to address the requirements of 32-bit microcontroller (MCU) product development, offering a higher-performance, more feature-rich and lower-power solution than that offered by competing cores based on the ARM® architecture. This paper outlines the design features that are implemented in MIPS® processor cores that contribute to their industry-leading performance. Additionally, we compare and contrast MCU design solutions based on the MIPS and ARM architectures. We will provide you with the substance beyond the hype, and key considerations for choosing a MIPS processor core.

Using Vivado with Xilinx Evaluation Boards

Learn how the board-aware features of the Vivado® Design suite can be used to quickly configure and implement designs targeting Xilinx Evaluation Boards. See how the IP Integrator presents all of the possible IP interfaces into the Board and how they can easily be configured and connected in your design. See how all of the logical and physical parameters and constraints are automatically assigned and passed to the downstream implementation tools.

First Virtex UltraScale FPGA Demonstration

Watch a demonstration of the first device in the industry's only 20nm high end family—the Virtex® UltraScale™ VU095 device—featuring GTY transceivers capable of 32.75G short reach and 28.21G backplane operation, ideal for implementing next generation 400G and 500G wired networking systems.

Motor Efficiency Depends Upon Power Factor

Electric motor efficiency is taking center stage these days not only because the potential power savings are significant, but also because the technology for achieving them is now available. This white paper discusses the factors that are critical in achieving overall system power savings, taking into consideration the rectifier that conditions input power from the AC mains and the variable frequency inverter drive electronics of the motor. Active power factor correction for the rectifier used in modern motor drives is required to keep the generated line harmonics within regulatory limits and reduce wasted power. Mixed-signal FPGAs, by doing many calculations in parallel, can perform better than other possible motor control and power factor correction implementations.

The Industry's First 20nm and UltraScale FPGAs and 3D ICs

The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system level performance for the most demanding applications.

SDSoC Development Environment: Estimation & Implementation

Part 1 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews the challenges in implementing a system in a Zynq® SoC device and how SDSoC helps resolve those challenges. Then the video shows a demo of SDSoC on an example design to generate performance estimate and run a full design implementation using those estimates, and verifying the results achieved on the evaluation board.

New Episode - Circular Placement for Multi-Channel Designs - Altium's Design Secret Video Series

Watch a selection of short videos featuring tips, tricks and processes to get the most out of designing with Altium.

Digital Predistortion for Base Station Power Amplifiers

In this episode of our new Chalk TalkHD series, Amelia Dalton talks to Todd Nelson from Linear Technology about how digital predistortion (DPD) can be used to save millions of dollars worth of power in base station designs. DPD is simple to apply, and has a dramatic impact on the power amplifier - the most power-hungry part of modern base stations. In this Chalk TalkHD you'll hear how DPD works and how you can apply it to your next design.


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