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Select the Right Performance for a 802.11ac/Advanced LTE AFE

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind choosing the right ADC in and Analog Front End for wireless (802.11ac and/or 3G/3G) communication systems. Learn more about Cadence IP at http://ip.cadence.com.

Using Low Cost, Non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

UltraScale Devices Integrated 100G Ethernet IP Demo

See a demonstration of the integrated 100G Ethernet MAC and CAUI-4 IP available on UltraScale™ devices. This IP offers savings of up to 80K LUTs and 90% power over a soft implementation and simplifies your design process and time to market by providing proven functionality.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

A Significant Technology Advancement in High-Speed Link Modeling and Simulation

This white paper describes how Altera's jitter/noise eye (JNEye) link analysis tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the requirements for accuracy and advanced simulation and modeling techniques.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Formal VIP for 100% Accurate Designs

In this week's Whiteboard Wednesdays video, Tom Hackett discusses formal verification IP (VIP), how it supports formal analysis, and how design engineers can leverage formal VIP to ensure their designs are 100% correct. Learn more about Cadence IP at http://ip.cadence.com.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

chalk talks

Adding Wi-Fi to Your FPGA Design - Building a Connected Device

In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.

Design @ MachXO2 Speed

Just about every design needs one - that magic, do-anything part that can connect nearly any two things together and can aggregate all those messy, left-over functions on our board. Today's low density PLDs have remarkable capabilities at a tiny cost and power budget. In this episode of Chalk Talk HD Amelia Dalton chats with Steve Hossner (Lattice Semiconductor) about the amazing capabilities of Lattice’s latest low density PLD line, the MachXO2.

Integrated Power and System Management

In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit

In this episode of Chalk TalkHD Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.

Intel Atom™ Processor with built-in Altera Arria® FPGA

In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.

Timing Closure in FPGA Designs Made Easy with PlanAhead

In this episode of Chalk TalkHD Amelia chats with Frederic Rivoallon of Xilinx and they attempt to unravel the mysteries of timing closure and reveal that yes, you can get timing closure right the first time in your next design.

latest papers and content

Select the Right Performance for a 802.11ac/Advanced LTE AFE

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind choosing the right ADC in and Analog Front End for wireless (802.11ac and/or 3G/3G) communication systems. Learn more about Cadence IP at http://ip.cadence.com.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Aldec Active HDL Datasheet

Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager. Active-HDL has interfaces to over 80 leading EDA tools, making it the most powerful environment. Check out the top features and product configurations to see if Active-HDL is right for you.

Formal VIP for 100% Accurate Designs

In this week's Whiteboard Wednesdays video, Tom Hackett discusses formal verification IP (VIP), how it supports formal analysis, and how design engineers can leverage formal VIP to ensure their designs are 100% correct. Learn more about Cadence IP at http://ip.cadence.com.

How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design. Learn more about Cadence IP at http://ip.cadence.com.

Reduce Project Schedules and Increase Quality using Model Driven Development for Design, Verification, and Test

This paper shows how Model Driven Development can address common challenges in the system design, verification & testing of complex systems. Project success requires that hardware, software, and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components, which often proves to be costly in terms of time, money, and engineering resources. This paper covers such solutions that reduce project schedule while improving product release quality.

Modernizing System Development

Allowing disconnected development and waiting until the latest program stages to perform systems integration and connect all the pieces is a high risk situation, yet one all too common in today’s product realization process. Bringing domain expertise together as appropriate throughout a project’s development process is imperative for project success.  This paper explores a more modern approach to system development built on a Model Driven Development (MDD) approach.

Successfully Designing FPGA-Based Systems

One key challenge in successfully designing FPGA-based systems is choosing the right FPGA for the design needs, and maximizing the use of FPGA resources. In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.

Addressing the “Power-Aware” Challenges of Memory Interface Designs

One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing high-speed memory interfaces. This paper assesses how modern tools can be used to address power-aware SI challenges with I/O modeling, interconnect modeling, simulation, and analysis.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis Tech Packet

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High Speed Data Acquisition and Software Defined Radio Made Simple

Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk TalkHD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems.

New MIPI Interfaces: Winners or Losers?

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a deeper look at the MIPI protocols that are the leading choice for certain mobile interfaces. Even though MIPI protocols are a top choice, however, they are being challenged by mobile versions of PCI Express and USB. Given this landscape, what does the future look like for MIPI and its challengers? Watch this short video to find out!

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

GEN2 Serial RapidIO and Low Cost, Low Power FPGAs

System designers will continue to be under pressure to produce higher performance systems yet maintain lower build and operational costs. DSP and Network Processing Unit (NPU) devices, coupled with low cost, low power FPGAs like the Lattice ECP3 that support Gen2 Serial RapidIO (SRIO), can provide an ideal platform for meeting these challenges.

Putting Low Power and Flexibility Where It Matters Most: Handheld Portable Applications

In the short span of three decades, electronics have not only proliferated in our world, but have also gotten smaller and more portable. The march of Moore’s Law has brought portability to the consumer, industrial, military, medical and other markets. Download this whitepaper to learn about Actel solutions for handheld portable applications.

Selecting an Operating System (OS) for Embedded Application

It seems these days, just about every embedded system has some type of operating system. And there are more options today as to which OS to choose. Is open source your best choice? What about a free RTOS? In this paper, learn the pros and cons of the many OS options available today and how to select the right OS for your next embedded project.

Protecting the FPGA Design From Common Threats

The global estimated loss to counterfeiting is expected to exceed U.S.$1.5 trillion in 2009. Counterfeiting impacts all businesses in all markets, from Gucci handbags to computer chips to proprietary algorithms. The threats to companies’ intellectual property (IP) grow as the global supply chain becomes increasingly complex. Security and protection in the global supply chain is critical to maintaining a competitive advantage, while in some cases it is required just to stay in business.

Balancing Performance, Power, and Cost with the Kintex-7 FPGAs

In the past, FPGA vendors commonly segmented their portfolios between "high-end" and "low-cost" devices. However, as developers have refined the way they leverage FPGA technologies, they have voiced the need for a "mid-range" solution, featuring high-end functionality and performance in a cost effective package. The Xilinx® Kintex™-7 family of FPGAs was developed for these applications, delivering the most balanced power and performance in the industry while providing high-end features, such as cutting-edge transceivers, integrated IP, and extensive DSP resources.

Open-Silicon—Cadence Integrated SPB Environment for a Successful On-Time Product Launch

Kavitha Nagarajan, Lead Engineer -- IC Package Design at Open Silicon, Inc., describes how the company leveraged the Cadence(r) Integrated SPB environment to successfully complete a complex project with a tight deadline. From the package feasibility study, design, electrical analysis and design-for-manufacturing, everything could be done inside the Cadence SPB environment. This led to a successful, on-time launch of the customer's product.

Easily Support WDR CMOS Image Sensor Processing with Low-Cost FPGAs

High-definition (HD) wide dynamic range (WDR) CMOS image sensors are ideal for applications like video surveillance cameras. And for the underlying technology, FPGAs are optimal because they deliver the high bandwidth these sensors demand. In this 7-minute video, you'll see how an FPGA-based platform easily performs complex image processing to support WDR CMOS image sensors.

ARM and Cadence Help SoC Designers Achieve Power, Performance, and Area Goals

William Orme, Strategic Marketing Manager at ARM, and Steve Brown, Director of Product Marketing at Cadence, describe the collaboration and use of the Cadence(r) Interconnect Workbench with ARM’s CoreLink(r) System IP to help SoC designers achieve their power, performance and area goals.

Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design

This application note describes two reference designs that demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet MegaCore® functions with on-board Marvell 88E1111 PHY chips. The reference designs provide flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks.

Strategic Considerations for Emerging SoC FPGAs (REVISED)

Semiconductor devices that integrate FPGA fabric, hardened CPU subsystems, and other hardened IP—SoC FPGAs—have reached a tipping point that will lead to their broad proliferation in the next decade, therefore offering many options for system designers. These SoC FPGAs complement the decade-long availability of soft-core CPUs and other soft IP for building systems on FPGAs. This white paper describes the emergence of system on a chip (SoC) FPGAs, the drivers behind that emergence, and strategic considerations for executive management and system designers when choosing these devices.

Solutions for Mixed-Signal SoC Verification

As SoC complexity grows and process nodes shrink, it’s no longer adequate to bolt together analog or digital “black boxes” that are presumed to be pre-verified. Complex analog/digital interactions can create functional errors, which delay tapeouts and lead to costly silicon re-spins. Cadence helps customers overcome these challenges with a fully integrated mixed-signal verification solution that spans basic mixed-signal simulation to comprehensive, metric-driven mixed-signal verification.

Analog Devices Raises Productivity with ModGen Tools

Watch this video to learn how Analog Devices ramped up engineering productivity using ModGen tools in Cadence's Virtuoso® Layout Suite solution. CAD engineer Eduard Raines explains how his team replaced time-consuming manual processes with an automated solution to create custom programs for high performance, highly matched design structures.

Introducing the UltraFAST Design Methodology Checklist

Learn how to access and perform the UltraFAST™ Design Methodology Checklist to ensure your design and design environment are optimized for the Vivado® Design Suite. The Checklist highlights many of the recommendations made in UG949: The UltraFast Design Methodology for the Vivado Design Suite. It consists of a series of questions with actions to take related to each phase of the design process. Ensuring your design and design process are optimized for Vivado can increase design performance and reduce time spent with design closure or understanding tool issues.


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