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Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Five Ways to Build Flexibility into Industrial Applications with FPGAs

System complexity continues to increase in industrial designs such as communications, motor control, I/O modules and image processing. Read how FPGAs offer the ability to integrate an entire SoC at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. Whether used as a coprocessor or SoC, FPGAs offer the following advantages for your industrial applications: · Design integration to simplify and reduce cost · Reprogrammability to adapt industrial designs to evolving protocols · Performance scaling to meet your system requirements. · Obsolescence protection through long FPGA life cycles and device migration

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

chalk talks

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

IP and Process Solutions for Energy-efficient PMICs

In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.

Integrated Power and System Management

In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Hardware/Software Co-Verification of ARM Processor-Based Designs

In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti of EvE about the latest in emulation technology and explains how you can use emulation to dramatically accelerate software development, which is becoming the most time-consuming part of SoC design.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.

Power Supply Management in High-Availability Systems

One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

latest papers and content

SDAccel Development Environment Demonstration

This video demonstrates the SDAccel™ development environment for acceleration using a standard X86_64 workstation containing an Alpha data ADM-PCIE-7V3 accelerator.

Introducing SDAccel Development Environment

The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Assertion-Based Emulation Using Veloce

This paper describes the assertion-based verification approach along with its benefits and uses. It further explains the advantages of emulation, especially for very large and complex SoCs, and how Veloce® assertion synthesis improves the emulation of SoCs that include assertions and helps reduce the time to verification closure. The Veloce compiler synthesizes logic for the assertions along with the design under test (DUT) and maps them into the emulator, making emulation faster.

SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors fabric behavior, and the Interconnect Workbench for performance analysis. The combined solution delivers functional verification along with latency and bandwidth analysis to fine-tune interconnect performance.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effecitvely, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

OrCAD Now – PSpice

This presentation is on the benefits of using PSpice® in an integrated OrCAD flow. For new users, it covers how to get started and where to find working examples. The next step is where to find specific models and how to create them if they’re not available anywhere. Finally it will go deeper into the tool to see how it can help us if we run into trouble by identifying parts that are close to failure.

Xilinx Product Teardown at ARM Tech Con: What's In There Besides Zynq SoCs?

Watch Steve Leibson, Editor of the Xilinx Xcell Daily Blog, moderate two product tear downs featuring the National Instruments Virtual Bench and the Cloudium Integrated Media Processing Platform.

Xilinx at ARM TechCon 2014: Booth demonstration presented by National Instruments

Eric Myers, Product Manager for Embedded Products, National Instruments, demonstrates the Airbus Smart Tools concept for their Factory of the Future using the NI System on Module (SOM).

TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification.

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Xilinx at ARM TechCon 2014: Booth demonstration presented by National Instruments

Eric Myers, Product Manager for Embedded Products, National Instruments, demonstrates the Airbus Smart Tools concept for their Factory of the Future using the NI System on Module (SOM).

Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs

With our Transceiver Signal Integrity Development Kit, Stratix V GX Edition and the Transceiver Toolkit tool in Quartus II software, you can easily and efficiently evaluate the performance of the high-speed serial transceivers in the Stratix V FPGA.

Unlock New Levels of Productivity for Your Design Using ISE Design Suite 12

In addition to the anticipated performance improvements commensurate with the production release of a Xilinx tool suite, the release of ISE v12 software unveils significant innovations with far-reaching potential. A new power-optimization capability called intelligent clock gating can reduce dynamic power by up to 30%. An innovation called design preservation vastly improves the user’s ability to achieve and maintain timing closure and design repeatability.

Overcome Copper Limits with Optical Interfaces

With today’s high-bandwidth, low-latency devices and associated applications—such as smart phones, tablets, HDTV, and 3DTV—computer and network system vendors endeavor to deliver systems that don’t significantly add to network or internet traffic congestion and latency. This document discusses how optical interface technology embedded in an FPGA overcomes the reach, power, port density, cost, and circuit board complexity challenges associated with discrete copper interconnects.

FPGA-Based Control for Electric Vehicle and Hybrid Electric Vehicle Power Electronics

The speed and flexibility of FPGAs are beneficial in high-performance power electronics control systems. This white paper describes the benefits of using FPGA-based control in a hybrid electric vehicle (hybrid EV) or electric vehicle (EV) drive system comprised of a variable-voltage control (VVC) or bidirectional DC-DC converter, 3-phase inverters, and interior permanent magnet (IPM) motor or generators. This paper also describes the implementation of VVC converter and the motor inverter control in an integrated simulation environment with Simulink and DSP Builder.

I/O Design Flexibility with the FPGA Mezzanine Card (FMC)

The FPGA’s inherent flexibility has proven indispensable for the creation of external I/O interfaces. However, unless I/O is implemented on a daughter card (mezzanine module), replacing the physical I/O components and connectors requires changing the FPGA board design. To avoid these costs, designers have historically relied on the PCI™ Mezzanine Card (PMC) and Switched Mezzanine Card (XMC) standards. The problem is that these were developed years ago for general purpose solutions such as single-board computers— not FPGAs.

MachXO PLDs in System Control Designs

Introduction Temperature measurement, current monitoring, power supply sequencing, fan control and fault logging are typical board control functions used in complex circuit designs. System designers are faced with continual pressure to meet their development schedules, and need to implement control functions with minimal effort and risk while maintaining maximum flexibility.

Accelerate Your Video Processing Application Using Reference Designs

Wouldn´t you like an integrated solution that makes developing broadcast infrastructure equipment easier and faster? Watch this new 9-minute video to learn about two development kits and reference designs that do just this.

SmartFusion2 SoC FPGA Demo: Error Detection and Correction of eSRAM Memory User’s Guide

This demo is intended to demonstrate the error detection and correction (EDAC) capabilities of SmartFusion®2 SoC FPGA on the embedded SRAM. The EDAC controllers implemented in SmartFusion2 SoC FPGAs support single error correction and double error detection (SECDED). All memories within the microcontroller subsystem (MSS) of the SmartFusion2 SoC FPGA are protected by SECDED.

Interface Additions to the e Language for Effective Communication with SystemC TLM 2.0 Models

Transaction-level models (TLMs) have a number of advantages—they are available earlier, they allow users to divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they can be used as reference models in advanced verification environments. New additions to e in the Cadence® Specman technology portfolio enable verification engineers to communicate efficiently with SystemC models that have TLM 2.0 interfaces.

Enabling Design Separation for High-Reliability and Information-Assurance Systems

Traditionally, system designs achieve reliability through redundancy, leading to increased component count, logic size, system power, and cost. Altera’s design separation feature meets these conflicting power, size, and functionality needs while maintaining high reliability and information assurance. The use of FPGAs has grown from the glue logic interfaces of the past to the advanced information-processing systems used by core Internet routers and high-performance computing systems.

Power Estimation and Management for MachXO2 Devices

A key requirement for many of today’s high volume FPGA applications is low power consumption. The MachXO2™ PLD provides many power-saving features including Power Controller, Bank Controller and Power Guard. This technical note provides users with detail for using the MachXO2 low power architectural features including power supply considerations and power estimations provided by the Power Calculator tool.

TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification.

Lowering The Total Cost of Ownership for Industrial Applications

Approximately one-third of embedded designers surveyed on the adoption and use of FPGAs for embedded applications responded that they perceived FPGAs as too expensive to use in their designs. However, a look at the total cost of ownership (TCO) at the system level (as measured by development, enhancement, replacement, and maintenance costs over the lifetime of the product) reveals that Altera FPGAs offer competitive and flexible alternatives to discrete MCU/DSP/ASSP products.

SmartFusion2 SoC FPGA Adaptive FIR Filter Demo User’s Guide

SmartFusion®2 SoC FPGA devices integrate a 4th generation flash-based FPGA fabric and an ARM® Cortex™-M3 processor. The SmartFusion2 SoC FPGA fabric includes embedded mathblocks, which are optimized specifically for DSP applications such as, finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast fourier transform (FFT) functions. Adaptive filters are widely used in different DSP application areas like communication, biomedical, audio/video processing because of their ability to adjust the filter coefficients according to adaptive algorithms and input signal characteristics.

Smarter Networks Backgrounder

Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. But just what do those words mean? It means that the FPGA fabric, the fundamental building block of all Xilinx silicon products—All Programmable FPGAs, 3D ICs, and SoCs—has reached a critical threshold at the 28nm process node. This threshold marks the transition where FPGAs have evolved to the point where they are large enough and fast enough to implement complete systems. At 28nm, Xilinx is capable of replacing entire ASSPs and ASICs, which means that a Xilinx All Programmable device equipped with the right IP and software may well be the only significant integrated circuit needed to implement many end products. Read the incontrovertible proof in this backgrounder.

Single-Event Effect Mitigation in RTAX-DSP Space-Flight FPGAs

When high-energy ions present in space strike the substrate of an IC, their impact can cause momentary current/voltage pulses in the IC’s circuitry. When these pulses are sufficient to change the data on the circuit, they are referred to collectively as single-event effects (SEEs).

Xilinx and ARM: Zynq-7000 All Programmable SoC

Ian Ferguson, VP of Segment Marketing at ARM, introduces the Zynq®-7000 All Programmable SoC as the result of a strong partnership between ARM and Xilinx. He discusses how Zynq is opening up new markets for ARM and is alleviating the need for a multi-chip solution in many applications. Ferguson also speaks to Zynq's compatibility with leading operating systems and tools, and challenges designers to develop new and creative ways to design with a Zynq-7000 SoC.


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