Search On Demand

 
 
 
 

Recommended Reading

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

What’s New in PSpice 16.6

In this webcast Matthew Harms demonstrates the new features in version 16.6 of Cadence PSpice. Matthew covers three major areas: productivity enhancements, core enhancements, and TCL Integration. This webcast covers most of these features with an explanation and a short demonstration.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Mixed Signal Verification: The Long and Winding Road

Verification of your mixed-signal design can be a nightmare, with clashing disciplines and engineering cultures, and challenging use-case requirements. In this episode of Chalk Talk, Amelia Dalton chats with Steve Carlson of Cadence Design Systems about a comprehensive approach to mixed-signal system verification.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Meet PPA and Turnaround Time Requirements at Advanced Nodes with Innovus Implementation System

Today's complex IC designs demand a new generation of high-capacity, high-performance implementation tools. In this episode of Chalk Talk, Amelia Dalton chats Yufeng Luo of Cadence Design Systems about the incredible innovations in Cadence's new Innovus implementation suite.

Accelerating Your Analog Output Design

Eventually, most of our designs need to control something in the real world. That means we have to bust out of our safe little digital realm, and drive some analog actuators or something similar. But, building that analog output section from scratch can be a real challenge. In this episode of Chalk Talk, Amelia Dalton talks to Bill Laumeister of Maxim Integrated about the Analog Output Design Accelerator Kit (MAXREFDES24EVSYS), a complete platform for easy evaluation that requires no lab equipment.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Inductance-to-Digital Converters Revolutionize Position & Rotation Sensing

Inductive sensing is a reliable, accurate, and robust technology for a wide variety of position, rotation, metal detection and spring compression measurement applications. In this episode of Chalk Talk, Amelia Dalton chats with Anjana Govil of Texas Instruments about how you can use inductance-to-digital converters to take advantage for inductive sensing in your next design.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

From Simulation to Emulation – A Fully Reusable UVM Framework

This paper introduces an acceleration-ready UVM framework and explains why it is needed and how to create it. Readers will learn how to write block-level UVM environments that can be reused directly in emulation for block, subsystem, and system level verification. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation.

Connecting ZYNQ-7000 All Programmable SoCs with TE Connectivity Interconnect Products

New SoCs like the Xilinx Zynq are changing the industry - with new levels of functionality, flexibility, performance, and power efficiency. But, to take advantage of this new technology you'll need connectivity solutions that are up to the task. In this episode of Chalk Talk, Amelia Dalton chats with Mark Bell from TE Connectivity about plugs, connectors, antennas, and other connectivity solutions for today's most demanding designs.

chalk talks

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.

Intel Atom™ Processor with built-in Altera Arria® FPGA

In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Effective Version Control for Electronic Design

When it comes to our hardware engineering projects, we need to keep our design data well organized. In the software world, this is accomplished with the help of version control systems. Unfortunately, most of us don’t learn version control for hardware design. In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how effective version control can help every step of the design process, enable team design, manage versions and configurations, and keep our project from spiraling out of control.

latest papers and content

Meet PPA and Turnaround Time Requirements at Advanced Nodes with Innovus Implementation System

Today's complex IC designs demand a new generation of high-capacity, high-performance implementation tools. In this episode of Chalk Talk, Amelia Dalton chats Yufeng Luo of Cadence Design Systems about the incredible innovations in Cadence's new Innovus implementation suite.

Inductance-to-Digital Converters Revolutionize Position & Rotation Sensing

Inductive sensing is a reliable, accurate, and robust technology for a wide variety of position, rotation, metal detection and spring compression measurement applications. In this episode of Chalk Talk, Amelia Dalton chats with Anjana Govil of Texas Instruments about how you can use inductance-to-digital converters to take advantage for inductive sensing in your next design.

Connecting ZYNQ-7000 All Programmable SoCs with TE Connectivity Interconnect Products

New SoCs like the Xilinx Zynq are changing the industry - with new levels of functionality, flexibility, performance, and power efficiency. But, to take advantage of this new technology you'll need connectivity solutions that are up to the task. In this episode of Chalk Talk, Amelia Dalton chats with Mark Bell from TE Connectivity about plugs, connectors, antennas, and other connectivity solutions for today's most demanding designs.

Zynq-7000 All Programmable SoC: Embedded Design Tutorial

To help accelerate your Zynq®-7000 All Programmable SoC embedded development, Xilinx has introduced a new Embedded Design Tutorial, a hands-on guide designed to help walk you through embedded system design. The guide provides opportunities to work with tools under discussion, examples and an explanation of what is happening behind the scenes.

UltraFast Embedded Design Methodology Guide (REVISED)

Xilinx is building on the success of its UltraFast™ Design Methodology with the new UltraFast Embedded Design Methodology Guide. The new Guide enables embedded design teams to improve productivity with a documented methodology for the creation of smarter systems leveraging Zynq®-7000 All Programmable SoCs.

Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs

Xilinx discusses how programmable logic provides the partial reconfiguration capabilities, large number of high speed analog IOs and mix signal capabilities to build high density, scalable and flexible 500G/1T line cards today.

Xilinx and Ixia present 400GE and 25GE testing solutions at OFC 2015

In this live presentation from OFC 2015, Xilinx talks with Ixia about how they surmounted the many obstacles to efficient 400GE and 25GE testing by leveraging Xilinx’s All Programmable devices to get the Ixia 400GE and 25GE tester families to market quickly. Presented by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.

i.MX 6SoloX – Freescale’s New Heterogeneous Multicore Applications Processor

Many applications today need both an applications processor AND a real-time MCU. But, most solutions don't offer both on the same chip. In this episode of Chalk Talk, Amelia Dalton chats with Amanda McGregor of Freescale about a new application processor that combines an ARM Cortex-A9 core with the efficiency and real-time capability of the Cortex-M4.

UltraScale Integrated 100G Ethernet IP for 10x10G and 4x25G

This video demonstrates how using an integrated Ethernet MAC can save power, integration time and logic utilization while delivering the highest possible flexibility. The UltraScale™ Integrated 100G Ethernet IP supports both CAUI-4 and CAUI-10 interfaces to CFP, CFP2, CFP4 and other pluggable optics. As shown in this video, the IP can easily and dynamically swap between interfaces.

Kintex UltraScale DSP Kit with 8 Lane JESD204B interface

The video highlights the Xilinx® Kintex® UltraScale™ FPGA Analog Devices JESD204B DSP Kit featuring the Xilinx Kintex UltraScale KCU105 development board with the KU40 device paired up with the Analog Devices AD-FMCDAQ2-EBZ high-speed analog FMC module. An 8 lane JESD204B interface is used to interface the data converters to the FPGA using GTX serial transceivers at the full 12.5 GSPS line rate. Xilinx devices are the world’s first to support the full JESD204B line rate across all device speed grades for mid-range JESD204B solutions, and the only all programmable solution available today at 20nm.

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

« Previous123456...38Next »

New To On Demand?

Registered users can access hundreds of whitepapers, demos, videos, webcasts and more. Sign up now.

Already a registered user? Log in here to access content.

subscribe to journal on demand weekly newsletter

more on demand

Partial Reconfiguration in Vivado

Learn how Partial Reconfiguration of 7 series devices allows users to dynamically change portions of a design while the rest of the design remains operational. This video provides an overview of the Vivado® Partial Reconfiguration solution, from features, benefits, and design considerations to a walkthrough of the flow in the Vivado Design Suite.

Spartan-6 FPGAs in Video Designs

In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.

Addressing the “Power-Aware” Challenges of Memory Interface Designs

One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing high-speed memory interfaces. This paper assesses how modern tools can be used to address power-aware SI challenges with I/O modeling, interconnect modeling, simulation, and analysis.

Unlock New Levels of Productivity for Your Design Using ISE Design Suite 12

In addition to the anticipated performance improvements commensurate with the production release of a Xilinx tool suite, the release of ISE v12 software unveils significant innovations with far-reaching potential. A new power-optimization capability called intelligent clock gating can reduce dynamic power by up to 30%. An innovation called design preservation vastly improves the user’s ability to achieve and maintain timing closure and design repeatability.

UltraFast™ Design Methodology Guide for the Vivado Design Suite

This Guide discusses a design methodology process to follow in order to achieve an efficient and quicker design implementation, and to derive the maximum value from Xilinx devices and tools.

Design Control, Data and Comparison with PADS Archive Management

Do you spend too much time archiving your designs, and later searching through archives for just that one project? Are your engineering reviews disorganized? Does your archive management flow store all the project files that you use? Files like libraries, reports, CAM data, etc.., not just design data? Are you able to quickly search archives, and compare and cross-probe between the schematic and layout files, or redline and append mark-up notes?

Proper archives are essential to back up and manage design data. A design-driven storage methodology promotes effective data backups, increasing productivity by efficiently creating, indexing, and restoring archives within a vault.

Xilinx SDNet: A New Way to Specify Network Hardware

This paper, written by The Linley Group, examines Xilinx’s SDNet specification environment and its role, both in defining elements in Software-Defined Networks, and in implementing reconfigurable network elements in both control plane and data plane.

Zynq-7000 All Programmable SoC: Embedded Design Tutorial

To help accelerate your Zynq®-7000 All Programmable SoC embedded development, Xilinx has introduced a new Embedded Design Tutorial, a hands-on guide designed to help walk you through embedded system design. The guide provides opportunities to work with tools under discussion, examples and an explanation of what is happening behind the scenes.

Wireless Base Station ZUC Block Cipher Implementation on Zynq SoCs

The Xilinx Zynq®-7000 All Programmable SoC provides a flexible platform that offers programmability for evolving technologies like LTE and new standards including, but not limited to, the ZUC algorithm. This white paper illustrates the advantages of the Zynq SoC-based design methodology using the Vivado® Design Suite, which facilitates an optimal hardware/software partitioning of the system functionality for better performance.

A Generation Ahead – Zynq-7000 Video

Xilinx Zynq®-7000 All Programmable SoCs enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability. Using the Zynq-7000 platform, you can design smarter systems with tightly coupled software based control and analytics with real time hardware based processing and optimized system interfaces — with vastly lower BOM costs, lower NRE costs, lower design risk, and of course much faster time to market.

UltraScale FPGAs PCIe Performance Demo

See performance demos of the integrated PCIe Gen3 block available in UltraScale™ FPGAs. First demo shows maximum data throughput across the PCIe link; demo #2 leverages an off the shelf DMA engine and software driver to represent a typical use case.

Building a Hardware and Software Project Targeting the Zynq ZC702 Evaluation Kit

Watch as we show you how easy it is to build a Zynq®-7000 All Programmable SoC hardware and software project, targeting the Zynq ZC702 Evaluation kit, using Vivado® Design Suite and board-aware IP Integrator (IPI). See the advantages of the board-aware features of Vivado and build a complete hardware and software design example in just a few minutes and download it to the ZC702 board.

The Power Management IC for the Intel® AtomTM Processor E6xx Series and Intel® Platform Controller Hub EG20T

Time to market, cost, board size constraints, reliability and design capabilities are among the motivating factors in choosing Power Management IC versus a discrete solution. However, a discrete solution allows design optimization, offers higher power efficiency, flexibility and is easy to debug. Often, it is not possible to determine which choice will be better without understanding the details of design requirement. This paper aims to discuss both the advantages and disadvantages of using Power Management IC versus a discrete solution on the Intel® AtomTM Processor E6xx series platform.

OrCAD Documentation Editor

See how the OrCAD Documentation Editor speeds the PCB documentation process while helping to avoid errors and ensure better communication.

Leveraging OCP for Cache Coherent Traffic Within an Embedded Multi-core Cluster

Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems becomes essential to ensure behavioral consistency. One solution to provide access consistency is the application of a memory coherence model such as MESI or MOESI within the L1 data cache hierarchy. For the MIPS Technologies MIPS32® 1004K™ Coherent Processing System (CPS), we applied Open Core Protocol (OCP) point-to-point connectivity to establish snoop-based coherence throughout the cluster. Following are principles of this communication model.

Empowering the Virtual Cluster

In this video, Nick Difiore explains how the capabilities of Xilinx FPGAs allow a switch from mechanical to electronic displays.

Reduce Verification Complexity in Low/Multi-Power Designs

The increasing demand for highly reliable products covers many industries, all process nodes, and almost all design implementations. To satisfy this demand, reliability requirements are growing in all market segments.Accurate and repeatable reliability verification is now a critical capability, both for advanced nodes and for increasingly complex products being produced at established nodes. Read more of this whitepaper to learn how to create an easy-to-use, automated verification solution for low-power and multi-power domain designs.

How to easily setup Calibre in Virtuoso for multiple cell windows

This video shows how to setup Calibre Interactive to quickly select from multiple cells open in Virtuoso. Previously there was not a convenient way to setup Calibre Interactive when you wanted to run Calibre in different cells that are simultaneously open in the same Cadence session but now the Layout Cell Browser capability in Calibre Interactive provides an easy and convenient way to select from multiple cells open in Virtuoso.


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register