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Design Data Management with PTC Windchill and Cadence Allegro PCB

Learn how PTC and Cadence have developed a unique collaboration environment to connect Allegro PCB design data with the Windchill PLM system for robust file management and check-in check-out capabilities.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

OrCAD Constraint Driven Design Flow

The OrCAD constraint driven flow provides a unique, fully integrated environment to define design intent and dynamically track compliance throughout the entire implementation process. This slideshow is demonstrating how to utilize the constraint driven flow in OrCAD to improve efficiency, reduce errors, and help ensure on-time product delivery.

Announcing ProtoCompiler for Multi-FPGA Prototyping

Prototyping Automation and Debug Software for HAPS FPGA-Based Prototyping Systems Improves Prototyping Performance

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Using Low Cost, Non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

The UltraScale Architecture for Highest Utilization and Superior Performance

The UltraScale™ architecture introduces many innovations over traditional FPGA architectures that increase performance and reduce power consumption. In this video, we will focus on enhancements to the routing, logic and implementation software that result in an architecture allowing for the device to be highly utilized while still maintaining performance, and keeping runtime low.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

A Methodology for High-Speed Nanometer Transceiver Verification, Validation, and Characterization

This paper provides a short introduction to a 20 nm transceiver implementation supporting data rates up to 28.1 Gbps, outlining the circuit verification challenges, and introducing a new methodology for circuit validation and characterization across operational, environmental, and process conditions. Details of the validation flow are provided along with the results obtained by using the new methodology.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Lowering the Total Cost of Ownership in Industrial Applications

This white paper uses a design example to demonstrate that FPGAs are not only a more flexible option than discrete MCU, DSP and ASSP products, but also provide a lower total cost of ownership (TCO) as measured by development, enhancement, replacement, and maintenance costs over the lifetime of a system.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

chalk talks

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

latest papers and content

Three Ways that Allegro TimingVision Environment Speeds Up Timing Closure of High-Speed PCB Interfaces

On advanced high-speed interfaces, timing closure can be an iterative process that can be time-consuming and frustrating. PCB designers need techniques and tools to make the process more efficient, so they can contribute to an overall faster time to market for the design. This article discusses three ways that the new Cadence Allegro TimingVision Environment speeds up timing closure of high-speed PCB interfaces.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Addressing the Advantages of Embedded LTE and Advanced LTE

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of embedding a LTE and Advanced LTE analog block on the SoC to support many of the mobile applications in the market today.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design

Wireless RFIC designers are expected to be experts on a variety of ever-changing wireless standards and protocols. They must also contend with time-consuming manual simulation setup and post-processing of the simulation results. This paper discusses how an advanced simulation methodology, involving characterization and modeling of a RFIC design, enhances both the speed and the accuracy of system-level performance verification of a wireless RFIC.

UltraScale Architecture: Highest Device Utilization, Performance, and Scalability

The UltraScale™ architecture provides numerous technical innovations to exceed the utilization and performance demands of next-generation applications, all while offering both architectural migration and package footprint migration for optimal design reuse.

The UltraScale Architecture for Highest Utilization and Superior Performance

The UltraScale™ architecture introduces many innovations over traditional FPGA architectures that increase performance and reduce power consumption. In this video, we will focus on enhancements to the routing, logic and implementation software that result in an architecture allowing for the device to be highly utilized while still maintaining performance, and keeping runtime low.

OrCAD Constraint Driven Design Flow

The OrCAD constraint driven flow provides a unique, fully integrated environment to define design intent and dynamically track compliance throughout the entire implementation process. This slideshow is demonstrating how to utilize the constraint driven flow in OrCAD to improve efficiency, reduce errors, and help ensure on-time product delivery.

Design Data Management with PTC Windchill and Cadence Allegro PCB

Learn how PTC and Cadence have developed a unique collaboration environment to connect Allegro PCB design data with the Windchill PLM system for robust file management and check-in check-out capabilities.

Consumer DRAM Trends

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends in today's consumer market. He deep dives into the comparison between LPDDR4 and DDR4 DRAM.

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How to easily setup Calibre in Virtuoso for multiple cell windows

This video shows how to setup Calibre Interactive to quickly select from multiple cells open in Virtuoso. Previously there was not a convenient way to setup Calibre Interactive when you wanted to run Calibre in different cells that are simultaneously open in the same Cadence session but now the Layout Cell Browser capability in Calibre Interactive provides an easy and convenient way to select from multiple cells open in Virtuoso.

Open-Silicon—2.2GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor

Shrikrishna Mehetre and Souvik Mazmunder from Open-Silicon talk about how they leveraged Cadence Encounter Technologies to reach 2.2GHz Performance on 28nm ARM(r) Dual-Core Cortex(r)-A9 Processor.

Navigating the FDA Approval Process for Your Software Based Medical Device

Understand how to get your product to market within product launch schedules. Review challenges companies face as they seek FDA approval and review guidance and resources to assist with successfully navigating the approval process. Learn about a number of important areas including premarket submissions, documentation, verification and validation (V&V), user experience and human factors design, and cybersecurity.  Presented by Steve Robertson with Mentor Graphics Embedded Software.  

Developing Multipoint Touch Screens and Panels With CPLDs

When a certain web-enabled multimedia smartphone hit the market in 2007, it transformed the way that consumers interact with their handheld devices. Especially engaging is the fluid touch-screen interface that allows users to access an array of applications or scroll through web pages with their fingertips. To develop such sophisticated interfaces with high I/O counts, ease of use, low power, and flexibility to support product differentiation, design with zero-power Altera MAX IIZ CPLDs.

Troubleshooting and Fast Fault Isolation with VTOS

Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.

Multi-Board Electrical and Thermal Co-Simulation Using PowerDC

Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.

A Tailored Approach to FPGA Process Selection

This white paper examines three categories of process characteristics, relates them to the internal structure of modern FPGAs, and then, in turn, looks at the impact the FPGAs have on the systems that employ them. In particular, a focus on the deployment of so-called FinFET transistors shows how Altera is exploiting Intel’s 14 nm Tri-Gate process to achieve a level of FPGA density, performance, and power efficiency not reachable at all on the planar FET roadmap.

Simpler, Smarter Platform for Differentiated Digital TVs

The Spartan-6 FPGA Consumer Video kit provides a simpler way to update and modify video algorithms, and incorporate new video standards such as DisplayPort and V-by-One-HS. The advanced integrated design environment allows designers to efficiently develop and test high speed serial interfaces like LVDS and TMDS and debug HDMI or DVI-based solutions. The Spartan-6 FPGA Consumer Video Kit offers everything designers need to implement features for today and tomorrow's market. Watch this short video to learn more.

UAV-to-Basestation Encryption

Sr. Defense Architect Jim Anderson shows how Xilinx defense-grade Virtex FPGAs enable the highest level of information assurance with Type-1 Single-chip Cryptography in a UAV application.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Mastering the Magic of Multi-Patterning

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. Successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs.

Xilinx 7 series FPGAs

Xilinx 7 series FPGAs offer breakthrough power, performance, & dramatically reduced development time.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

Taming the Challenges of 20nm Custom/Analog Design

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers.

Vault-driven Electronics Design Whitepaper

The ‘endgame’ for any board design is to generate and manage data from that design for building the physical object captured by that design – and with the utmost integrity. However, the need to ensure high-integrity data often walks hand-in-hand with layers of bureaucratic ‘red tape’, resulting in the designer being confined to design according to formalized processes, locking down design changes to ensure minimal impact to the integrity of the design data.

Designing Polyphase DPD Solutions with 28nm FPGAs

This white paper describes how to design an efficient polyphase and non-polyphase digital predistortion (DPD) feed-forward path solution with Altera® 28nm FPGAs, especially the Arria® V family of FPGAs. In addition, a resource usage and power comparison between different architectures is provided to facilitate design tradeoffs.

Productivity Enhancements in OrCAD PCB Editor

This short video provides a compilation of recent productivity improvements added to OrCAD PCB Editor such as 3D Viewing, Multi Trace Routing, Arc Editing, and more.

All Programmable Abstractions Backgrounder

New All Programmable Abstractions initiative improves productivity of hardware designers and empowers systems and software developers to directly leverage Xilinx All Programmable devices. These abstractions have already proven to accelerate development of complex FPGAs and SoCs up to 15X over traditional RTL flows. To learn how you and your development team can take advantage of the right abstraction to fit your design needs, read the backgrounder.


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