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Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Library Creation Solutions

As designs become more complex, it's important to identify opportunities to enhance design processes. Designers need an efficient way to create accurate, complex, schematic symbols and PCB footprints. EMA Design Automation has a solution to fill that need with an automated, efficient, process for creating component symbol and footprint data.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Advanced System Management with Analog Non-volatile FPGAs

A system management device is critical to the successful power up, configuration, maintenance and power down of the system. As system complexity increases, the requirements of these devices are growing and features such as instant-on, analog capability, and flexibility are crucial. Read how a robust system management design incorporates a wide variety of tasks in both the analog and digital domain including power rail management, environmental condition management, and analytics for diagnostics and prognostics.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance. Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applications

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

chalk talks

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

Enabling New Applications with NFC Connectivity and Energy Harvesting

In this episode of Chalk TalkHD Amelia chats with Greg Proehl (STMicroelectronics) about the basics of NFC technology, and they explore some interesting NFC applications as well as cool and innovative new NFC solutions from ST - including one with energy harvesting capability.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

latest papers and content

The Rise of Serial Memory and the Future of DDR

With no plans emerging to define a "DDR5" specification, the entire memory landscape is going to change over the coming years. Serial memory technologies like Hybrid Memory Cube (HMC) and other schemes still in the pipeline can be expected to fill the memory needs of the future. From the beginning, Xilinx has engineered its UltraScale™ devices and platforms with the future in mind, providing a seamless transition to these newly emerging serial memory technologies.

The Application of FPGAs for Wireless Base-Station Connectivity

This white paper addresses the application of Xilinx FPGA technology to the implementation of internal communication networks within wireless base stations. This is a critical element of the system design within a range of base-station architectures, including conventional macrocell, high-density cell sites, CRAN configurations, and AAA configurations.

Library Creation Solutions

As designs become more complex, it's important to identify opportunities to enhance design processes. Designers need an efficient way to create accurate, complex, schematic symbols and PCB footprints. EMA Design Automation has a solution to fill that need with an automated, efficient, process for creating component symbol and footprint data.

What’s New in PSpice 16.6

In this webcast Matthew Harms demonstrates the new features in version 16.6 of Cadence PSpice. Matthew covers three major areas: productivity enhancements, core enhancements, and TCL Integration. This webcast covers most of these features with an explanation and a short demonstration.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs

This Virtex® UltraScale™ FPGA demonstration shows the newly integrated Interlaken IP core running at 150Gb/s over 12 lanes. By integrating Interlaken, Xilinx is able to reduce power consumption, logic utilization, and design complexity for one of the most popular protocols in networking today.

Virtex UltraScale VU440 FPGA Demonstration

See the new Virtex® UltraScale™ VU440, the world’s largest FPGA, in action being used to prototype 10 ARM® Cortex®-A9 CPUs.

Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applications

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.

New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance. Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

What’s New in Capture 16.6

OrCAD 16.6 is here. Watch this free webcast to learn what's new in the latest release of OrCAD Capture, including enhancements in productivity, usability, and features. Highlights: • Database Enhancements • CIS Explorer Improvements & Customization • Tcl Expansion • SI Integration • Improved Symbol Creation

PSpice Modeling

Join EMA for an on-demand webinar to learn more about part modeling in Cadence® PSpice®, the industry’s #1 analog simulator. We will highlight features such as creating parts from a datasheet, using vendor supplied models, and modifying existing parts.

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Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!

Mastering the Magic of Multi-Patterning

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. Successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Repeatable Results with Design Preservation

Increasingly, FPGA designs are no longer just the “glue logic” of the past; they are becoming more complex every year, often incorporating challenging IP such as PCI Express® cores. The complex modules in newer designs, even when not changing, can present difficulties when attempting to meet qualityof-result (QoR) requirements. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well.

Simpler, Smarter Platform for Differentiated Digital TVs

The Spartan-6 FPGA Consumer Video kit provides a simpler way to update and modify video algorithms, and incorporate new video standards such as DisplayPort and V-by-One-HS. The advanced integrated design environment allows designers to efficiently develop and test high speed serial interfaces like LVDS and TMDS and debug HDMI or DVI-based solutions. The Spartan-6 FPGA Consumer Video Kit offers everything designers need to implement features for today and tomorrow's market. Watch this short video to learn more.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

Xilinx and Huawei Discuss 400GE Networking

In this live presentation at OFC 2014, Huawei and Xilinx discuss how they are working together to solve the challenges associated with 400GE network readiness. This presentation also discusses the key technologies in 400GE and how programmable technology is playing a key role to expedite the development and deployment of Huawei's future IP router products in the networking infrastructure.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

SystemVision® Multi-discipline System Verification Datasheet

The SystemVision multi-discipline collaboration environment lets you explore concepts, validate performance specifications, investigate architectural partitions, and integrate implementation-level details, all in an easy-to-use virtual prototyping environment. Focus on a single design domain, or combine multiple domains, for full-system verification.

Xilinx and ARM: Zynq-7000 All Programmable SoC

Ian Ferguson, VP of Segment Marketing at ARM, introduces the Zynq®-7000 All Programmable SoC as the result of a strong partnership between ARM and Xilinx. He discusses how Zynq is opening up new markets for ARM and is alleviating the need for a multi-chip solution in many applications. Ferguson also speaks to Zynq's compatibility with leading operating systems and tools, and challenges designers to develop new and creative ways to design with a Zynq-7000 SoC.

Implementing High-Speed DDR3 Memory Controllers in a Mid-Range FPGA

Implementing a high-speed, high-efficiency DDR3 memory controller in a FPGA is a formidable task. Until recently, only a few high-end (read: expensive) FPGAs supported the building blocks needed to interface reliably to high speed DDR3 memory devices. However, a new generation of mid-range FPGAs now provides the building blocks, a high-speed FPGA fabric, clock management resources and the I/O structures needed to implement the next generation DDR3 memory controllers.

Five Ways to Build Flexibility into Industrial Applications with FPGAs

As industrial system complexity increases, FPGAs offer the ability to integrate an entire system on a chip (SoC), at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. This document describes using an Altera industrial-grade FPGA as a coprocessor or SoC to bring flexibility to industrial applications. Providing a single, highly integrated platform for multiple industrial products, Altera FPGAs can substantially reduce development time and risk.

Linking Early Mechatronic System Analysis to Physical Testing

Comprehensive testing is critical for many systems; however, system design and test development are often at opposite ends of a project’s schedule. Benefits accrue in improved system quality and on-time delivery when design and test are pursued concurrently.  Recent advances in modeling, simulation, and test technology provide the ability to link system design to system test well in advance of prototype availability. This paper describes the technologies required to improve test quality and reduce development cycles.

Implementing FPGA Design with OpenCL – A Future Look

Are you using FPGAs to accelerate your system? Altera is exploring a new technology for FPGAs that will provide exciting and significant productivity gains for your high-performance systems. Watch this webcast to find out about Altera’s Open Computing Language (OpenCL™) program for FPGAs.

5 Easy Steps to Building an Embedded Processor System Inside an FPGA

You may know about the cost and performance advantages of designing systems on a programmable chip. But did you know how easy it is to do? Learn how by watching this new 8-minute video. You'll learn, step by step, how to build your microcontroller functionality into an FPGA in just minutes and see the compact, low-cost BeMicro FPGA-based MCU Evaluation Board in action. You'll also find out how easy it is to design with the configurable 32-bit Nios® II embedded processor.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Meeting the Low Power Imperative at 28nm (REVISED)

This white paper describes how Altera’s 28nm devices enable product developers to control power consumption in today’s increasingly power sensitive applications.

Beyond the Hype: MIPS® - the Processor for MCUs

A market leader in the Digital Home and Networking sectors, MIPS has adapted its industry-standard MIPS32® architecture to address the requirements of 32-bit microcontroller (MCU) product development, offering a higher-performance, more feature-rich and lower-power solution than that offered by competing cores based on the ARM® architecture. This paper outlines the design features that are implemented in MIPS® processor cores that contribute to their industry-leading performance. Additionally, we compare and contrast MCU design solutions based on the MIPS and ARM architectures. We will provide you with the substance beyond the hype, and key considerations for choosing a MIPS processor core.


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