Search On Demand

 
 
 
 

Recommended Reading

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Multiplying the Value of 20nm with UltraScale Devices: Doing More for Less

Xilinx is multiplying the value of 20nm with the UltraScale™ architecture and associated family of FPGAs and 3D ICs. Whether viewed from almost every attribute at the chip level or viewed when integrating multiple chips into one or fewer chips at the system level, you will find compelling value metrics as you migrate to an UltraScale solution. UltraScale architecture and Vivado® Design Suite are co-optimized to enable a device utilization target of 90%, which can result in up to a 30% effective cost advantage for the next generation of smarter, high performance systems in: Packet processing: Multi-hundred gigabit throughput Waveform processing: Multi-teraMAC throughput Image and video processing: 8K4K image and video processing and transport High performance computing: Multi-teraflop throughput Learn More about potential chip and system level value multipliers.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

Speed IP Bring-up and SoC Validation with HAPS-DX

Neil Songcuan, Sr. Product Marketing Manager, introduces the newest member of the HAPS family, HAPS Developer Express (HAPS-DX) and its features to speed IP bring-up and SoC validation

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

Troy Scott, Product Marketing Manager, and Peter Zhang, R&D Engineer, explain RTL debug features available in ProtoCompiler.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Lowering the Total Cost of Ownership in Industrial Applications

This white paper uses a design example to demonstrate that FPGAs are not only a more flexible option than discrete MCU, DSP and ASSP products, but also provide a lower total cost of ownership (TCO) as measured by development, enhancement, replacement, and maintenance costs over the lifetime of a system.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

chalk talks

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Verification Methodologies (Made Easy)

Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.

Digital Predistortion for Base Station Power Amplifiers

In this episode of our new Chalk TalkHD series, Amelia Dalton talks to Todd Nelson from Linear Technology about how digital predistortion (DPD) can be used to save millions of dollars worth of power in base station designs. DPD is simple to apply, and has a dramatic impact on the power amplifier - the most power-hungry part of modern base stations. In this Chalk TalkHD you'll hear how DPD works and how you can apply it to your next design.

latest papers and content

Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

How to automatically replace LEF abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

How to waive DRC results using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Multi-Board Electrical and Thermal Co-Simulation Using PowerDC

Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.

TimingDesigner: Complex Diagrams

This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

How to easily setup Calibre in Virtuoso for multiple cell windows

This video shows how to setup Calibre Interactive to quickly select from multiple cells open in Virtuoso. Previously there was not a convenient way to setup Calibre Interactive when you wanted to run Calibre in different cells that are simultaneously open in the same Cadence session but now the Layout Cell Browser capability in Calibre Interactive provides an easy and convenient way to select from multiple cells open in Virtuoso.

How to Debug Double Patterning results using Calibre RealTime

This video shows how to easily debug Double Patterning results in Calibre RealTime by using the CTO file to assign different highlight colors to the warning and conflict ring results and to the mask1 and mask2 output layers.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

« Previous123456...60Next »

New To On Demand?

Registered users can access hundreds of whitepapers, demos, videos, webcasts and more. Sign up now.

Already a registered user? Log in here to access content.

subscribe to journal on demand weekly newsletter

more on demand

Radar Processing: FPGAs or GPUs?

While general-purpose graphics processing units (GP-GPUs) offer high rates of peak floating-point operations per second (FLOPs), FPGAs now offer competing levels of floating-point processing. Moreover, Altera® FPGAs now support OpenCL™, a leading programming language used with GPUs.

Enabling FPGA Plug-and-Play Design with the AXI-4 Common Interconnect

This video offers details of Xilinx support for the AXI-4 Common Interconnect and highlights the benefits of increased designer productivity, greater IP availability, and extended flexibility to achieve performance and system goals. Using the Xilinx Targeted Design Platforms to illustrate these benefits, Xilinx technical experts describe how support for the AXI-4 Common Interconnect is the cornerstone for the move to FPGA Plug-and-Play design.

Optimizing and Maintaining a High-Performing Design Environment

To maximize your investment in EDA tools, your infrastructure and processes must be optimized for growing and frequently changing design needs. Cadence Client Technology Solutions is dedicated to enhancing EDA tool performance, ensuring stability, and removing critical bottlenecks. Through close collaboration with hundreds of customers worldwide, we have unique insight into environmental conditions and how best to maintain a high-performing design environment.

Improve Reliability with Accurate Voltage-Aware DRC

Consumer expectations for longer device operations at sustained performance levels means designing for reliability is no longer an optional product feature, but a necessary and integral part of a product’s specifications. Power challenges in today's integrated circuit (IC) designs create a significant increase in verification complexity. Read more of this whitepaper to learn how to go beyond the traditional triumvirate of DRC, LVS, and ERC to provide robust reliability verification throughout the design flow and ensure maximum design efficiency.

FPGA Coprocessing Evolution: Sustained Performance Approaches Peak Performance

FPGA architecture allows for many algorithm implementations where the sustained performance is much closer to the device’s peak performance when compared to quad-core CPUs or GPGPUs. The strong benchmarking results from FPGA accelerators will continue to improve with appropriate focus on the silicon, arithmetic, and library foundations. As even the largest FPGAs currently consume less than 30W of power, FPGA roadmaps are well below datacenter power and cooling limitations.

Building a Hardware and Software Project Targeting the Zynq ZC702 Evaluation Kit

Watch as we show you how easy it is to build a Zynq®-7000 All Programmable SoC hardware and software project, targeting the Zynq ZC702 Evaluation kit, using Vivado® Design Suite and board-aware IP Integrator (IPI). See the advantages of the board-aware features of Vivado and build a complete hardware and software design example in just a few minutes and download it to the ZC702 board.

I/O Design Flexibility with the FPGA Mezzanine Card (FMC)

The FPGA’s inherent flexibility has proven indispensable for the creation of external I/O interfaces. However, unless I/O is implemented on a daughter card (mezzanine module), replacing the physical I/O components and connectors requires changing the FPGA board design. To avoid these costs, designers have historically relied on the PCI™ Mezzanine Card (PMC) and Switched Mezzanine Card (XMC) standards. The problem is that these were developed years ago for general purpose solutions such as single-board computers— not FPGAs.

Streamline Your Video Processing Apps with Design Examples

Wouldn’t it be great if you could develop your video processing applications faster? You can with a complete suite of ready-to-use video processing functions. These functions are ready to be dropped into your design and connected through open Avalon® Streaming interfaces. Watch this 5-minute video for a demo that shows you a low-cost touch screen-based development kit running two design examples based on these functions.

Building an IP Surveillance Camera System with a Low-Cost FPGA (REVISED)

Current market trends in video surveillance present a number of challenges to be addressed, including the move from analog to digital cameras, conversion to high-definition (HD) video, adoption of Wide Dynamic Range (WDR) sensors, and Internet Protocol (IP) connectivity for control and data streams. This white paper describes the IP Surveillance Camera Reference Design and shows how the entire system is built using a low-cost Altera® Cyclone® III FPGA

Next-Generation Packaging for CRM Applications

With smaller electronics, more options can be fit into the package, allowing for features such as RF transceivers for wireless communication, advanced sensors to optimally time pacing and defibrillation shocks and backup systems in case the main system fails. While integrated circuits (ICs) have taken advantage of advances in dense packaging, such as die stacking, in most cases the discrete components remain unchanged. Market pressures are now forcing improvements in the current discrete packaging.

Xilinx DSP Targeted Design Platforms Deliver Performance, Price, Power, and Productivity

Digital signal processing (DSP) design starts have surpassed every other segment of the processing arena. Consequently, the demand for differentiated value in every aspect of DSP design has never been higher, increasing pressure on the teams tasked to build winning designs in record time. Xilinx conceived the Targeted Design Platform to address this challenge—the necessity to do more with less, to remove risk wherever possible, and to differentiate in order to excel.

Targeting Zynq Using Vivado IP Integrator

Learn how Vivado® IP Integrator can be used to rapidly configure a Zynq® processor and connect it via AXI4 to a video accelerator running in the programmable fabric of the device. Using built in board aware design rule checks and designer automation, Vivado can greatly improve user productivity.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

28 nm Characterization Lab Walk-Through

Liam Madden, Vice President of Silicon Technology takes you through the characterization lab at Xilinx discussing 28nm technology.

Simulating Zynq BFM design using Synopsys VCS in Vivado

Learn how to run simulation with ZYNQ® BFM IPI design using Synopsys VCS simulator in Vivado®. We will provide a demonstration on how to compile simulation libraries, generate simulation scripts for an IP or an entire project and then run simulation.

Implementing Always-On Audio

In this week’s Whiteboard Wednesdays episode, Gerard Andrews, from the Tensilica Audio DSP Group at Cadence, discusses always-on audio functionality. Gerard details features like voice trigger, sensor fusion, and low-power audio playback, and explains how Cadence’s HiFi DSP solution can help you successfully implement always-on audio technology in today’s mobile devices.

Design Made Easy With the SmartFusion Customizable System-on-Chip and State of the Art Software Tools

Since the early years of embedded processor design and FPGA design, silicon advancement and design techniques for each have evolved independently. In the real world there are many FPGA designs without embedded processors and many embedded systems that neither have nor need an FPGA. This leads to two very distinct design flows, styles, and engineering disciplines. The relatively recent addition of SmartFusion® customizable system-on-chip (cSoC) devices adds the complexity of analog into the mix.

Putting Low Power and Flexibility Where It Matters Most: Handheld Portable Applications

In the short span of three decades, electronics have not only proliferated in our world, but have also gotten smaller and more portable. The march of Moore’s Law has brought portability to the consumer, industrial, military, medical and other markets. Download this whitepaper to learn about Actel solutions for handheld portable applications.


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register