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Library Creation Solutions

As designs become more complex, it's important to identify opportunities to enhance design processes. Designers need an efficient way to create accurate, complex, schematic symbols and PCB footprints. EMA Design Automation has a solution to fill that need with an automated, efficient, process for creating component symbol and footprint data.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Achieve DDR3 Signoff With Power-Aware Timing Analysis

Cadence and EMA have collaborated to provide a unique power-aware DDR timing sign off flow for complete cycle-accurate system level simulation and analysis. You can now sign off on your entire DDR interface with total confidence.

Software Debug Using Lauterbach TRACE32 on Veloce with Physical and Virtual Probes

This whitepaper discusses how the Lauterbach tools and Veloce emulator can work in both virtual and physical environments to give a consistent view for software debug. By connecting to either the virtual debug interfaces (used in models and simulators) or by connecting to physical debug hardware (used by FPGA prototypes and silicon), the Veloce emulator allows users to bridge the gap between the two environments, choosing the one applicable to their needs and position in the design flow.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

SDSoC Development Environment: Estimation & Implementation

Part 1 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews the challenges in implementing a system in a Zynq® SoC device and how SDSoC helps resolve those challenges. Then the video shows a demo of SDSoC on an example design to generate performance estimate and run a full design implementation using those estimates, and verifying the results achieved on the evaluation board.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

chalk talks

IP and Process Solutions for Energy-efficient PMICs

In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Power Supply Management in High-Availability Systems

One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit

In this episode of Chalk TalkHD Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

latest papers and content

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

SDSoC Development Environment: Estimation & Implementation

Part 1 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews the challenges in implementing a system in a Zynq® SoC device and how SDSoC helps resolve those challenges. Then the video shows a demo of SDSoC on an example design to generate performance estimate and run a full design implementation using those estimates, and verifying the results achieved on the evaluation board.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

SDSoc Development Environment Backgrounder

This backgrounder describes the features and benefits of the SDSoC™ Development Environment. The SDSoC development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use an Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

Introducing the SDSoC Development Environment

The SDSoC™ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

UltraScale + 16nm Technology and Portfolio Backgrounder

Learn about new memory, 3D-on-3D, and multi-processing SoC (MPSoC) technologies introduced in Xilinx’s new 16nm UltraScale+™ portfolio of FPGAs, 3D ICs and MPSoCs, collectively delivering a generation ahead of value for next generation systems. This backgrounder describes the innovations introduced in the Kintex®, Virtex®, and Zynq® UltraScale+ families and how they address a broad broad range of next generation applications, including LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT) applications.

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more on demand

Parameterizable Content-Addressable Memory

This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software. The CAM reference design should be used for all new FPGA designs targeting Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP FPGAs, and newer architectures. All the features and interfaces included in the reference design are backward compatible with the LogiCORE™ IP CAM v6.1 core. In addition, because the reference design is provided in plain-text VHDL format, the implementation of the function is fully visible, allowing for easy debug and modification of the code.

UltraScale FPGAs Power Advantage

See how you can address power savings and provide more performance headroom in your next generation designs with the UltraScale™ FPGAs.

Stacked Silicon Interconnect Technology Implemented in ISE Design Suite

This video features stacked silicon interconnect technology and how it is implemented in the ISE design suite. Liam Madden, VP of Silicon Technology explains...

Power Consumption at 40 and 45nm

At 40 and 45 nm process nodes, power quite often becomes the primary factor for FPGA selection. This white paper details how Xilinx designed for low power in its new Spartan®-6 and Virtex®-6 FPGA families, achieving dramatic power reductions over previous generation devices.

Xilinx at NAB 2014 | OmniTek Ultra 4K Tool Box

David Ackroyd, Business Development Director for OmniTek demonstrates an an Ultra 4K Tool Box that includes conversions from 4K to/from SD including quad 3G-SDI.

Introducing the Avnet TI OMAP/Spartan-6 FPGA Co-Processing Kit

FPGA-based co-processing is 15X faster than traditional processor/DSP systems. Conventional system design methods face stiff challenges to meet the requirements of today’s ultra-high performance applications. This video explains how the TI OMAP/Spartan-6 FPGA Co-Processing Kit delivers breakthrough system performance by integrating and optimizing the key strengths of high performance FPGAs, system control processing, and digital signal processing, all within one single environment.

The Rise of Serial Memory and the Future of DDR

With no plans emerging to define a "DDR5" specification, the entire memory landscape is going to change over the coming years. Serial memory technologies like Hybrid Memory Cube (HMC) and other schemes still in the pipeline can be expected to fill the memory needs of the future. From the beginning, Xilinx has engineered its UltraScale™ devices and platforms with the future in mind, providing a seamless transition to these newly emerging serial memory technologies.

Injecting Automation into Verification - FPGA Market Trends

This webinar is a manager’s introduction to trends in the FPGA market and provide a business perspective on how companies are crossing the FPGA design verification barrier. Learn the common tools, techniques and learning aids that make an effective FPGA verification process. We will discuss the business and technical merits of common techniques and processes that your team can start deploying now.

Leveraging Power Leadership at 28nm with Xilinx 7 Series FPGAs

In this new whitepaper, learn the most effective methods for minimizing FPGA power consumption with Xilinx's industry-leading power solutions. Real-world design examples showcasing Xilinx power estimation and optimization methods are discussed.

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

Enabling High-Speed Radio Designs With Xilinx All Programmable FPGAs and SoCs

This white paper describes the capabilities of Xilinx® 7 series All Programmable FPGAs and SoCs to implement high-clock-rate signal processing functionality typically used by the datapath of digital radio applications.

MicroBlaze Overview

Learn basics of MicroBlaze™ such as key features, architecture and customization options. We'll also review some of the available MicroBlaze-based collateral.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Why Do I Need a Customizable ARM-based SoC?

In this episode of Chalk TalkHD Amelia chats with Todd Koelling of Altera about what’s inside these new SoC FPGAs and how you can get started designing with them.

Zynq UltraScale+ MPSoC Overview

Building on the industry’s first All Programmable SoC, Xilinx is enabling a generation ahead of integration and intelligence with unprecedented levels of heterogeneous multi-processing system on chip and delivering 5X system-level performance per watt. By combining the right engines for the right tasks, Zynq® UltraScale+™ MPSoC provides a flexible, scalable processing platform with the highest levels of security and safety.

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.


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