Search On Demand

 
 
 
 


Search Results

 

Enabling High-Precision, High-Performance DSP With Variable-Precision DSP Architecture

High-performance signal-processing designs increasingly require higher than 18-bit precision and even a range of precisions across the datapath. You're probably seeing these requirements in traditional digital signal processing (DSP) functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), emerging matrix functions, and in custom signal-processing datapaths.

Enabling High-Precision DSP Applications with the FPGA Industry’s First Variable-Precision Architecture

The silicon DSP architecture of the FPGA can make a big difference when implementing complex signal-processing algorithms. Altera’s Stratix V FPGAs, with the variable-precision DSP block architecture, are the only programmable devices that efficiently support many different precision levels, including floating-point implementations. Also, with a 64-bit cascade bus and accumulator, the designer does not have to sacrifice precision when the algorithm implementation requires multiple DSP blocks.

See PCI Express Hard IP Demo on Low-Cost FPGA

Concerned about power consumption and device cost? Watch this 7-minute video to learn about a development kit featuring a low-cost FPGA that addresses both of these challenges. What's more, the FPGA family features the only low-cost device with PCI Express x4 functionality.

Extending Transceiver Leadership at 28nm

Efficiently supporting ever-increasing system bandwidth needs by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This paper is an architectural exploration of SERDES challenges and solutions for 12.5-Gbps backplanes and next-generation optical modules at 28 Gbps. It describes the direction of the 10- to 28-Gbps transceiver industry, highlights challenges, and introduces 28-nm silicon and productivity solutions that address these challenges.

Extending Transceiver Leadership at 28nm

As next-generation applications and systems continue driving up I/O bandwidth demands, transceivers are evolving to meet these requirements. The latest-generation transceivers deliver the highest data rates, at up to 28 Gbps, at the lowest power for applications such as 100 Gigabit Ethernet systems. In this 40-minute webcast, you'll get a close look at key transceiver capabilities in our 28-nm Stratix® V FPGAs.

Introducing Stratix V FPGAs: Built for Bandwidth

While supporting increasingly demanding bandwidth requirements, your products also need to meet stringent cost and power budgets. Altera's new 28-nm Stratix® V FPGAs and HardCopy® V ASICs deliver groundbreaking innovations addressing the challenges of next-generation designs.

Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs

Faced with higher capital expenditure, higher operating expenditure, and shrinking revenue growth, service providers are turning to 100-Gbit OTN solutions to scale their current 10-Gbit-based networks. However, there are large numbers of legacy systems operating at lower data rates, which need to be plugged into the emerging optical infrastructure using 100-Gbit OTN muxponders. Stratix V FPGAs contain key innovations that directly address the needs of 100-Gbit OTN muxponder solutions.

Integrating 100-GbE Switching Solutions on 28-nm FPGAs

Because today’s single-chip-based architectures are unable to meet this demand for increased bandwidth and complexity, there is a need to develop efficient algorithms and switching architectures to meet the high-speed network requirements. Stratix V FPGAs enable hardware designers to integrate true 100-GbE components for next-generation switches and routers that ensure QoS while balancing the distribution of data through the system.

Enabling Improved Image Format Conversion with FPGAs

To support the accelerating image format conversion to FPGAs, Altera has developed a 1080p video design framework, described in this white paper, that makes it easy for system designers to develop a custom image format conversion signal chain. The image format conversion reference design discussed can be used as a starting point and modified to develop custom video processing applications. This design is hardware-verified and is available to qualified customers.

Reduce Total System Cost in Portable Applications Using MAX II CPLDs

Traditionally, portable system designers have used ASICs and ASSPs to implement memory interfaces, I/O expansion, power-on sequencing, discrete logic functions, display, and other functions. Cost limitations, power and cooling restrictions, and board space requirements often limit the use of PLDs in these applications. Today, however, innovations in CPLDs in power reduction, cost optimization, and small form-factor packaging allow PLDs to replace or augment ASICs, ASSPs, and discrete devices.

Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register