Implementing DSP datapaths with different performance, precision, IP, and development flows is challenging and labor intensive. As more and more high-performance DSP datapaths are implemented on FPGAs, Altera has developed a complete DSP solutions portfolio at 28 nm to address these challenges and speed up the design cycle for FPGA-based applications. This white paper discusses the different components of this portfolio and how they come together to accelerate the implementation of a DSP design.
Over 70% of designs on Altera® FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of building external memory solutions with Altera FPGAs, including application needs, memory capabilities of Altera FPGAs, and device and IP selection. Also discussed is the modular style of the memory components, comprised of Altera’s controller and PHY offerings with circuit and calibration features.
Implementing Altera’s VIP Suite of MegaCore® functions, for sensor control and various image-processing capabilities, and Imagize’s FP-5500 compact video-processing engine, for sensor processing and image fusion, on Altera® Cyclone® IV FPGAs can kick-start development efforts for next-generation EO/IR and display systems, as well as provide a canned solution for the “boring” aspects of system design, leaving the designer free to innovate on value-add functions.
High-performance signal-processing designs increasingly require higher than 18-bit precision and even a range of precisions across the datapath. You're probably seeing these requirements in traditional digital signal processing (DSP) functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), emerging matrix functions, and in custom signal-processing datapaths.
The silicon DSP architecture of the FPGA can make a big difference when implementing complex signal-processing algorithms. Altera’s Stratix V FPGAs, with the variable-precision DSP block architecture, are the only programmable devices that efficiently support many different precision levels, including floating-point implementations. Also, with a 64-bit cascade bus and accumulator, the designer does not have to sacrifice precision when the algorithm implementation requires multiple DSP blocks.
Concerned about power consumption and device cost? Watch this 7-minute video to learn about a development kit featuring a low-cost FPGA that addresses both of these challenges. What's more, the FPGA family features the only low-cost device with PCI Express x4 functionality.
As next-generation applications and systems continue driving up I/O bandwidth demands, transceivers are evolving to meet these requirements. The latest-generation transceivers deliver the highest data rates, at up to 28 Gbps, at the lowest power for applications such as 100 Gigabit Ethernet systems. In this 40-minute webcast, you'll get a close look at key transceiver capabilities in our 28-nm Stratix® V FPGAs.
Efficiently supporting ever-increasing system bandwidth needs by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This paper is an architectural exploration of SERDES challenges and solutions for 12.5-Gbps backplanes and next-generation optical modules at 28 Gbps. It describes the direction of the 10- to 28-Gbps transceiver industry, highlights challenges, and introduces 28-nm silicon and productivity solutions that address these challenges.
While supporting increasingly demanding bandwidth requirements, your products also need to meet stringent cost and power budgets. Altera's new 28-nm Stratix® V FPGAs and HardCopy® V ASICs deliver groundbreaking innovations addressing the challenges of next-generation designs.
Because today’s single-chip-based architectures are unable to meet this demand for increased bandwidth and complexity, there is a need to develop efficient algorithms and switching architectures to meet the high-speed network requirements. Stratix V FPGAs enable hardware designers to integrate true 100-GbE components for next-generation switches and routers that ensure QoS while balancing the distribution of data through the system.