Search On Demand

 
 
 
 

Recommended Reading

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

VeriSilicon and Cadence Customer Success Story

With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

USB Controller Connectivity

In this week's Whiteboard Wednesday video, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC), and how they improve connectivity between multiple USB applications. Learn more about Cadence IP at http://ip.cadence.com.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Hardware in the Loop from the MATLAB/Simulink Environment

This white paper describes the tools, design flow, and verification of systems using Altera(r) FPGAs. It discusses the techniques of software simulation and hardware testing, and the challenges associated with them. This paper also describes the advantages of using the Hardware in the Loop (HIL) tool, which is part of Altera's software tools, to simplify software simulation and hardware testing in a variety of applications.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

chalk talks

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Adding Wi-Fi to Your FPGA Design - Building a Connected Device

In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Introducing SmartFusion2 FPGAs

In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about Microsemi's biggest FPGA announcement this year - SmartFusion2. This new family can do things we never expected from Microsemi's non-volatile FPGAs. Watch this Chalk Talk to learn what it's all about.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit

In this episode of Chalk TalkHD Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.

Industrial Temperature Measurement Solutions

Many industrial designs need data from sensors such as temperature probes. But, getting from the analog world of probe signals to the digital world where the magic happens can be a tedious and tricky process. In this episode of Chalk Talk, Amelia Dalton talks with Sean Long of Maxim Integrated about an easy way to connect up sensors such as temperature probes in your next industrial design.

latest papers and content

VeriSilicon and Cadence Customer Success Story

With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.

ASIC Prototyping Simplified

To use current solutions for application-specific integrated circuit (ASIC) prototyping using field-programmable gate arrays (FPGAs), you either have to create custom boards or buy off-the-shelf FPGA boards. Off-the-shelf boards don’t satisfy the requirements for complex systems on chips (SOCs), and they’re expensive and lack scalability. Cadence Allegro FPGA System Planner fills the gap, offering a simplified approach to ASIC prototyping.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through the extraction, implementation, and final signoff loop for fastest timing closure.

USB Controller Connectivity

In this week's Whiteboard Wednesday video, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed Interchip Connectivity (SSIC), and how they improve connectivity between multiple USB applications. Learn more about Cadence IP at http://ip.cadence.com.

A Methodology to Manage Mechatronic Development in Medical Electronic Products

Model Driven Development (MDD) dramatically reduces the risks of complex mechatronic system development, increases productivity within an FDA-regulated process, and automates collaborative development among disparate teams. An MDD flow gives the system integrator an effective platform from which to communicate the overall system requirements and can also tie project management into development and automate mundane/time-consuming tasks, so designers can spend their time doing what they do best – designing.

New Approach to Manage Electrical Complexity

Today's competitive and challenging environment, thought-leaders are recommending a shift to systems engineering. Using a systems engineering approach could help OEMs maintain product quality, reduce costs, manage change, and achieve time to market. This paper talks about applying systems engineering principles using the Capital tool suite to address these issues.

Verification Made Easy with Memory Models

In this week's Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Faster Wiring and Harness Design

Does your electrical design software just do the basics? Or does it take the complexities of today's designs out of the task and save you time and money? This short white paper outlines the top ten highlights of how new tools make wiring and harness design faster and better.

EWIS Requirements: The Business Challenge

Without proper planning and the evolution of their business to efficiently deal with the EWIS mandates, companies could find themselves in a very costly situation. This paper investigates the issues surrounding EWIS compliance and methods to minimize both cost and potential program delays.

EDS Design Tools for Electric Vehicles

This paper explores how challenges for electric vehicles from battery placement to electrical distribution to eliminating crosstalk between high- and low-level signals can be solved with advanced EDS software. Also see how design environments incorporate features for designer to address product plans and answer tomorrow's demand for fully electric vehicles.

« Previous123456...55Next »

New To On Demand?

Registered users can access hundreds of whitepapers, demos, videos, webcasts and more. Sign up now.

Already a registered user? Log in here to access content.

subscribe to journal on demand weekly newsletter

more on demand

Hardware Accelerated H.264 Video Encoding using VAAPI on the Intel® Atom™ Processor E6xx Series

The Intel® Atom™ Processor E6xx Series for the embedded devices market includes the POWERVR* VXE core that provides video encoding capabilities, allowing to encode high definition video streams in the highly compressed H.264 format with a very low main CPU utilization, releasing the general purpose processor for other parallel workloads. This processor feature is available to application developers by means of the open Video Acceleration API (VAAPI [1]). This paper explains how the VAAPI can be applied to a real time video encoding task, explaining the VAAPI function calls flow, and the corresponding parameters.

Advanced Timing Exception Multicycle Path Constraints

Learn Xilinx recommendations for constraining multicycle path constraints. Understand and apply multicycle path exception constraints in your design.

Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs

Faced with higher capital expenditure, higher operating expenditure, and shrinking revenue growth, service providers are turning to 100-Gbit OTN solutions to scale their current 10-Gbit-based networks. However, there are large numbers of legacy systems operating at lower data rates, which need to be plugged into the emerging optical infrastructure using 100-Gbit OTN muxponders. Stratix V FPGAs contain key innovations that directly address the needs of 100-Gbit OTN muxponder solutions.

8 Reasons to Use FPGAs in IEC 61508 Functional Safety Applications

FPGAs are increasingly replacing electronic components used for industrial applications, thus international standards like the IEC 61508 have to support these evolving technology trends if they want to keep their relevance. This white paper gives developers eight simple reasons why FPGAs should be chosen in their IEC 61508 functional safety project versus standard microcontrollers or DSPs.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Meeting the Performance and Power Imperative of the Zettabyte Era with Generation

Today’s Information and Communications Technology (ICT) equipment developers face a daunting problem in addressing exponential growth in bandwidth demand while minimizing power consumption. This white paper outlines the performance and power requirements for next-generation programmable logic solutions to meet the demands of the growing ICT sector by leveraging multiple process technologies and revolutionary approaches to transistor design, new architectures, and comprehensive device-level power features.

Achieving Lowest System Power with Low-Power 28nm FPGAs

Lowest system power can be achieved by utilizing low-power FPGAs, which can be more power efficient than processors, ASSPs, and ASICs. When evaluating low-power FPGAs, key considerations include the power efficiency of the process technology, architectures and features, system interconnects, and EDA software. Altera® Cyclone® V FPGAs excel at all of the above metrics, and do so at the lowest system cost.

Five Ways to Build Flexibility into Industrial Applications with FPGAs

As industrial system complexity increases, FPGAs offer the ability to integrate an entire system on a chip (SoC), at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. This document describes using an Altera industrial-grade FPGA as a coprocessor or SoC to bring flexibility to industrial applications. Providing a single, highly integrated platform for multiple industrial products, Altera FPGAs can substantially reduce development time and risk.

OpenCL on FPGAs for GPU Programmers

In this white paper, Acceleware introduces parallel programming targeting Altera® FPGAs using the OpenCL™ framework to graphics processing unit (GPU) programmers. This white paper provides a brief overview of OpenCL, discusses the Altera FPGA architecture and its benefits, and explains how OpenCL kernels are executed and optimized on FPGAs versus GPUs.

Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency

The programmable imperative—the critical need to achieve more with less, to reduce risks wherever possible, and to quickly create differentiated products using programmable hardware design platforms—is driving the search for FPGA-based solutions that provide the capacity, lower power, and higher bandwidth with which users can create the system-level functionality currently delivered by ASICs and ASSPs. Download this whitepaper to learn more.

Reducing Switching Power with Intelligent Clock Gating

The intelligent clock-gating optimization feature introduced in ISE Design Suite v12 greatly simplifies the effort to reduce dynamic power in FPGA designs. The traditional approach to clock-gating optimization used in ASIC design presupposes an intimate knowledge of the design, thereby virtually precluding optimization of legacy and third-party IP blocks. New tools, new steps, and complex timing analyses are typically required to compensate for the inevitable new “gated clocks” and the changes in logic that are produced.

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

Debugging Machine Check Exceptions on Embedded IA Platforms

Embedded systems must be able to detect, recover from and report errors. This is a critical feature during debugging and also for quality control after product manufacturing has commenced. Advanced error handling is especially important for embedded systems. This white paper presents a step-by-step approach to debugging machine check exceptions and understanding their causes are resolving errors in embedded Intel® architecture platforms.

SmartFusion2 SoC FPGA Adaptive FIR Filter Demo User’s Guide

SmartFusion®2 SoC FPGA devices integrate a 4th generation flash-based FPGA fabric and an ARM® Cortex™-M3 processor. The SmartFusion2 SoC FPGA fabric includes embedded mathblocks, which are optimized specifically for DSP applications such as, finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast fourier transform (FFT) functions. Adaptive filters are widely used in different DSP application areas like communication, biomedical, audio/video processing because of their ability to adjust the filter coefficients according to adaptive algorithms and input signal characteristics.

Reducing Total System Cost with Low-Power 28nm FPGAs

Altera® Cyclone® V FPGAs help designers reduce total system cost in a number of ways. Designers benefit not only from TSMC’s 28-nm Low Power (28LP) manufacturing process, but also from the architectural decisions that have gone into the Cyclone V device family and the array of powerful productivity-enhancing tools featured in Altera’s design tool ecosystem. With Cyclone V FPGAs, customers not only enjoy the lowest cost of ownership in the industry, but the widest array of low-cost parts available—from 25K logic elements (LE) to 301K LEs—and the only 28-nm solution under 100K LEs.

Drive the Automotive Market with a Distinct Advantage: Xilinx Automotive Spartan-6 FPGAs

Just about 10 years ago, you could count on one hand the number of electronic systems in an automobile. Today, it is difficult to find a single system in a car that isn't electronic or at least electromechanical, as car manufacturers look beyond engine block size and body design to electronics to differentiate their offerings. Xilinx(r) Automotive (XA) Spartan(r) FPGAs are playing an increasingly important role in this auto electronics revolution.

Managing Image Data in Automotive Infotainment Applications Using Low Cost PLDs

7:1 LVS interfaces are popular in auto infotainment imaging applications due to their cost and power advantages. Lattice MachXO2 PLDs can be deployed in driver assistance systems to manage the display, scaling and rotation of images from the cameras. The devices can dynamically switch between camera images and can combine the images as well. Check out this whitepaper to learn more.


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register