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Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Accelerating Your Analog Output Design

Eventually, most of our designs need to control something in the real world. That means we have to bust out of our safe little digital realm, and drive some analog actuators or something similar. But, building that analog output section from scratch can be a real challenge. In this episode of Chalk Talk, Amelia Dalton talks to Bill Laumeister of Maxim Integrated about the Analog Output Design Accelerator Kit (MAXREFDES24EVSYS), a complete platform for easy evaluation that requires no lab equipment.

OrCAD Constraint Driven Design Flow

The OrCAD constraint driven flow provides a unique, fully integrated environment to define design intent and dynamically track compliance throughout the entire implementation process. This slideshow is demonstrating how to utilize the constraint driven flow in OrCAD to improve efficiency, reduce errors, and help ensure on-time product delivery.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Zynq UltraScale+ MPSoC Overview

Building on the industry’s first All Programmable SoC, Xilinx is enabling a generation ahead of integration and intelligence with unprecedented levels of heterogeneous multi-processing system on chip and delivering 5X system-level performance per watt. By combining the right engines for the right tasks, Zynq® UltraScale+™ MPSoC provides a flexible, scalable processing platform with the highest levels of security and safety.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Mixed Signal Verification: The Long and Winding Road

Verification of your mixed-signal design can be a nightmare, with clashing disciplines and engineering cultures, and challenging use-case requirements. In this episode of Chalk Talk, Amelia Dalton chats with Steve Carlson of Cadence Design Systems about a comprehensive approach to mixed-signal system verification.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Component Data Management with OrCAD CIS & CIP 5.0

Keeping your component library up to date and accurate can be quite a challenge. Learn how EMA and Cadence are enabling design teams to define, populate, and manage a shared corporate library that will ensure all users have access to the right parts when they need them.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

chalk talks

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Integrated Design Environment for FPGA

Do you find that FPGA design flows can get a bit confusing and difficult to manage? What we really need is an integrated design environment that will help us keep our design activities organized. In this episode of Chalk TalkHD Amelia chats with Satyam Jani from Aldec about integrated design environments (IDEs) for FPGA design, why FPGA designers need a vendor-independent IDE, and how an FPGA-centric IDE can help us get through our design flow quite a bit more easily.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Value of Power Modules

Today, the cool kids aren’t using discrete components for power anymore. Nope. They’re using power modules. In this episode of Chalk TalkHD Amelia chats with Rich Nowakowski and Kevin Beals (Texas Instruments) about power modules, and why they’re the best solution for a wide range of design projects.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

latest papers and content

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

SDSoC Development Environment: Estimation & Implementation

Part 1 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews the challenges in implementing a system in a Zynq® SoC device and how SDSoC helps resolve those challenges. Then the video shows a demo of SDSoC on an example design to generate performance estimate and run a full design implementation using those estimates, and verifying the results achieved on the evaluation board.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

SDSoc Development Environment Backgrounder

This backgrounder describes the features and benefits of the SDSoC™ Development Environment. The SDSoC development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use an Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

Introducing the SDSoC Development Environment

The SDSoC™ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment.

Cadence Perspec System Verifier SW Driven SoC Verification Automation

To verify your next system design, you'll need a lot of use cases. But, creating, tracking, sharing, and running those use cases can be a nightmare. In this episode of Chalk Talk, Amelia Dalton chats with Larry Melling of Cadence Design Systems about the new Cadence Perspec System Verifier and how you can take advantage of its power and flexibility in your system-level design verification.

Multiplying the Value of 16nm with UltraScale+ Devices: Staying a Generation Ahead

Xilinx is multiplying the value of 16nm with UltraScale+™ FPGAs, 3D ICs, and MPSoCs through key memory, 3D-on-3D, and multi-processing technologies and by leveraging the successful UltraScale architecture at 20nm. This paper describes in detail how to leverage key processing elements, connectivity interfaces, and other domain-optimized capabilities in the latest UltraScale+ portfolio for a broad range of application domains including wireless & waveform processing, packet processing & transport, video & image processing, high performance computing, and connected control.

UltraScale + 16nm Technology and Portfolio Backgrounder

Learn about new memory, 3D-on-3D, and multi-processing SoC (MPSoC) technologies introduced in Xilinx’s new 16nm UltraScale+™ portfolio of FPGAs, 3D ICs and MPSoCs, collectively delivering a generation ahead of value for next generation systems. This backgrounder describes the innovations introduced in the Kintex®, Virtex®, and Zynq® UltraScale+ families and how they address a broad broad range of next generation applications, including LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT) applications.

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The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

The UltraFast Design Methodology for the Vivado Design Suite

The UltraFast™ Design Methodology is a comprehensive design methodology enabling accelerated and predictable design cycles, delivered through the Vivado® Design Suite, a methodology guide, design checklist, self-training video, instructor-led courses, and third party tools & IP cores.

An Introduction to Rigid-Flex PCB Design Best Practices

More designers increasingly face project requirements for densely populated electronic circuits including pressures to reduce manufacturing times and costs. To meet these requirements, design teams have increasingly turned to 3D rigid-flex circuits to meet their project’s performance and production requirements.

High Speed Data Acquisition and Software Defined Radio Made Simple

Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk TalkHD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

9 Reasons Why The Vivado Design Suite Accelerates Design Productivity

Does your development team need to create complex, competitive, next-generation systems in a hurry? Download the new technical backgrounder and explore the 9 ways the Vivado® Design Suite improves your productivity.

World's First 28nm FPGA from Xilinx Shows Key 10Gbps SERDES Functionality

The first-ever 28nm FPGA demonstrates major design functionality within the first 48 hours, including 10Gbps eye quality.

FPGA Reliability and the Sunspot Cycle (REVISED)

What if your design had to go close to the sun? Would you be comfortable? Engineers design for system-level reliability when creating complex electronic systems. System reliability is dependent on a number of factors, including the reliability of the individual semiconductor devices selected for each design. Radiation effects impact device reliability in terrestrial as well as space applications. By choosing FPGA components judiciously, designers can significantly enhance the operational reliability and stability of any system.

Zynq UltraScale+ MPSoC Overview

Building on the industry’s first All Programmable SoC, Xilinx is enabling a generation ahead of integration and intelligence with unprecedented levels of heterogeneous multi-processing system on chip and delivering 5X system-level performance per watt. By combining the right engines for the right tasks, Zynq® UltraScale+™ MPSoC provides a flexible, scalable processing platform with the highest levels of security and safety.

Injecting Automation into Verification - Assertions

What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

Vivado IP Integrator Backgrounder

Accelerating the development of smarter systems requires levels of automation that go beyond RTL-level design. With the introduction of the Vivado™ Design Suite 2013.1, Xilinx delivers a SoC-strength, IP- and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation.

Xilinx Agile Mixed Signal

In this episode of Chalk TalkHD Amelia chats with Steve Logan (Xilinx ) and they're going to tell you all about Agile Mixed Signal, and how it can dramatically improve the capabilities of your next FPGA design.

Integrated Power and System Management

In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.

World's Smallest FPGAs Solve 4 Big Problems

In this episode of Chalk Talk, Amelia chats with Gordon Hands (Lattice Semiconductor) about some awesomely tiny FPGAs that bring the power of programmable logic into devices like cell phones, tablets, and other power and form factor sensitive applications.

Automotive Driver Assistance Systems: Using the Processing Power of FPGAs

Xilinx FPGAs offer a low cost, but flexible solution to meet multiple end customer requirements for differing levels of complexity in Automotive Instrumentation Design.

PSpice Modeling

Join EMA for an on-demand webinar to learn more about part modeling in Cadence® PSpice®, the industry’s #1 analog simulator. We will highlight features such as creating parts from a datasheet, using vendor supplied models, and modifying existing parts.

Understanding Single Event Effects (SEEs) in FPGAs

With the increasing popularity of programmable logic, FPGAs are finding their way into many applications that were once the territory of ASICs and ASSPs. At the same time, process nodes are shrinking and logic density is increasing, meaning that more of the system can be implemented in a single device. As programmable logic finds its way into avionics, communications and medical applications, designers face demands for increased reliability and safety over many of the traditional markets for FPGAs.

Hardware Programmability

Learn how FPGAs allow you to customize for your specific needs while enabling you to protect your differentiation in the marketplace.


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