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Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs

This Virtex® UltraScale™ FPGA demonstration shows the newly integrated Interlaken IP core running at 150Gb/s over 12 lanes. By integrating Interlaken, Xilinx is able to reduce power consumption, logic utilization, and design complexity for one of the most popular protocols in networking today.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

FPGA Product Support and EOL as Past Performance Indicators

This white paper presents the factors that lead to product obsolescence decisions made by FPGA vendors and how you can use this knowledge to craft obsolescence risk mitigation plans. This paper also introduces the idea of exercising Past Performance Assessments of FPGA vendors as both a risk and cost factor in making FPGA selection in military system design.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Function Enablement with 8-bit PIC Microcontrollers

For a lot of mainstream applications these days, 32-bit or even 16-bit processors are serious overkill. You can get great performance, smaller footprints, lower power consumption, and lower cost using 8-bit devices. In this episode of Chalk Talk, Amelia Dalton talks with Wayne Freeman of Microchip Technology about function enablement with 8-bit MCUs.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance. Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

PSpice Modeling

Join EMA for an on-demand webinar to learn more about part modeling in Cadence® PSpice®, the industry’s #1 analog simulator. We will highlight features such as creating parts from a datasheet, using vendor supplied models, and modifying existing parts.

Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applications

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Power-Aware Verification in Mixed-Signal Simulation

This paper presents the basic concepts of power-aware verification in mixed-signal simulation and applies them to the verification of a tire pressure monitoring system SoC, with the power architecture described in UPF. Many SoCs are mixed-signal in nature and have power-regulation functionality on the chip. Verifying such designs with mixed-signal simulation in power-aware mode complements digital verification by producing accurate results for the power management and analog units of a design.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

chalk talks

Getting Started Using Kintex-7 FPGAs for DSP

In this episode of Chalk TalkHD Amelia chats with Tom Hill of Xilinx about their new Kintex-7 DSP development kits that will finally get you onto the rocket-coaster of FPGA-powered DSP.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

Power Supply Management in High-Availability Systems

One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Maximize Design Productivity With PCIe/104 FPGA/Processor

In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

GLOBALFOUNDRIES RFCMOS Solutions and Catena WiFi Solutions

In this episode of Chalk TalkHD Amelia Dalton chats with Fayyaz Singaporewala (GLOBALFOUNDRIES) and Mats Carlsson (Catena) about how to get that scary RF portion of your next design done in a snap.

latest papers and content

Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs

This Virtex® UltraScale™ FPGA demonstration shows the newly integrated Interlaken IP core running at 150Gb/s over 12 lanes. By integrating Interlaken, Xilinx is able to reduce power consumption, logic utilization, and design complexity for one of the most popular protocols in networking today.

Virtex UltraScale VU440 FPGA Demonstration

See the new Virtex® UltraScale™ VU440, the world’s largest FPGA, in action being used to prototype 10 ARM® Cortex®-A9 CPUs.

Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applications

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.

New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance. Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

What’s New in Capture 16.6

OrCAD 16.6 is here. Watch this free webcast to learn what's new in the latest release of OrCAD Capture, including enhancements in productivity, usability, and features. Highlights: • Database Enhancements • CIS Explorer Improvements & Customization • Tcl Expansion • SI Integration • Improved Symbol Creation

PSpice Modeling

Join EMA for an on-demand webinar to learn more about part modeling in Cadence® PSpice®, the industry’s #1 analog simulator. We will highlight features such as creating parts from a datasheet, using vendor supplied models, and modifying existing parts.

MathWorks Connects to Hardware

The Maker movement is exploding right now, and most of the cool projects require doing some math. In this episode of Chalk Talk, Amelia Dalton chats with Amnon Gai of The MathWorks about using the powerful capabilities of MATLAB and Simulink in anything from your next maker hobby project to full-blown industrial designs.

TimingDesigner 9.3

Meeting system timing is a major challenge for today’s high-speed digital interfaces. Sr. Applications Engineer Jerry Long, will show how TimingDesigner provides an interactive timing analysis environment that delivers fast and accurate results for timing critical designs.

CircuitSpace 5.0: Discover Why Design Reuse Has Never Been Easier or More Flexible

This webinar is designed for Hardware Engineers and PCB Designers requiring an easy to use, flexible, and comprehensive design reuse methodology to coexist with their current OrCAD and Allegro PCB design tools. It is intended for new users as well as current users of EMA CircuitSpace software and focuses on front-to-back reuse methodologies and incorporates the new and enhanced features of version 5.0. Learn how the CircuitSpace 5.0 feature set can expedite your PCB layout process.

Soundwire Audio Interface

In this week's Whiteboard Wednesdays video, the first of a two-part series, Charles Qi highlights the new MIPI audio interface standard, Soundwire. Charles details how Soundwire supports new audio applications and can connect to multiple audio interface devices.

Achieve DDR3 Signoff With Power-Aware Timing Analysis

Cadence and EMA have collaborated to provide a unique power-aware DDR timing sign off flow for complete cycle-accurate system level simulation and analysis. You can now sign off on your entire DDR interface with total confidence.

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Altera's 28-nm FPGAs Optimized for Broadcast Video Applications

Increasing industry demand to deliver HD video channels requires studio equipment providers to deliver integrated products that provide the required bandwidth and processing power, while minimizing cost and power. This paper describes how Altera’s 40-nm and 28-nm FPGAs are tailored to help deliver highly-integrated, HD studio equipment products. The paper provides an analysis of the performance requirements, resource utilization, and power consumption characteristics for the format conversion of multiple video channels.

Achieving SerDes Interoperability on Altera’s 28nm FPGAs Using Introspect ESP

Introspect Technology has implemented its award-winning Introspect ESP embedded signal integrity analyzer on Altera’s high-end 28nm transceiver FPGAs. The result was a game-changing ability to achieve link optimization and interoperability on complex system boards containing a multitude of SerDes links. This white paper describes the various Introspect and Altera® technologies involved and illustrates, with real-life examples, the ability to self-measure, self-optimize, and self-repair SerDes links and systems.

DO-254 Requirements Traceability with Spec-TRACER

In this episode of Chalk TalkHD Amelia chats with Louie de Luna about Aldec's new Spec-TRACER tool and how Spec-TRACER helps you navigate your way through your design flow - from beginning to end, from requirements to verification.

Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach

The market trends for medical endoscopy systems present a variety of challenges, such as the need for increased functionality, higher definition, improved processing performance, and smaller profiles. This white paper describes Altera’s solution using the 1080p Video Design Framework, DSP building blocks, reference designs, and Stratix® V, Cyclone® V, and Arria® V FPGAs.

How to Effectively Manage Timing of FPGA Design Flow

When combined with advances in FPGA technologies for interface design efforts, EMA TimingDesigner can simplify design issues and provide advanced accurate control of virtually any interface. From simple SRAM interface protocols to high-speed source synchronous interface protocols, TimingDesigner allows designers to identify potential timing problems early in the design process and thereby providing the greatest opportunity to get the timing right the first time. This white paper will show you how to effectively integrate TimingDesigner with Xilinx and Altera Development Systems.

New MIPI Interfaces: Winners or Losers?

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a deeper look at the MIPI protocols that are the leading choice for certain mobile interfaces. Even though MIPI protocols are a top choice, however, they are being challenged by mobile versions of PCI Express and USB. Given this landscape, what does the future look like for MIPI and its challengers? Watch this short video to find out!

Single-Event Upsets (SEUs) and Medical Devices

Medical devices are not only susceptible to nature’s cosmic rays, but also must operate in radiation environments found in modern medical facilities. As evidence of these effects mounts, designers of medical devices must now also consider SEU susceptibility when choosing the technology that will form the basis for their products. This paper defines what the risks are and explains ways to mitigate and avoid these risks within programmable logic.

Memory Testing 101 – Avoid the Train Wreck

Memory is fundamental to the “sanity” of an embedded system. Inadequate memory testing is posing critical challenges to designers and indirectly manifesting considerable consequences at some of the biggest names in the electronics business. Today’s embedded systems consist of multiple memory types including SDRAM, LPDDR2, DDR3, FLASH, EEPROM and more, along with multiple protocols including GPIO, PCI, SPI and I2C. This paper will review a comprehensive and flexible Verification and Test Operating System (VTOS™) solution that includes a suite of memory tests that verifies the design for correctness and production readiness.

Test Vehicle Demonstration Of Stacked Silicon Interconnect Technology

This video features a hardware setup of a test vehicle of stacked silicon interconnect technology. Liam Madden, VP of Silicon Technology at Xilinx explains...

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Accelerating SoC FPGA Design in Complex Embedded Systems

The SoC FPGA design is a new device that incorporates both FPGA and microcontroller subsystem on a single device. As these devices capabilities extend to high speed serial and DDR memory interfaces, and high performance FPGA fabric with DSP processing, the architecture within the device requires an advanced tool methodology to simplify the designer’s experience and accelerate time-to-market. System Builder accomplishes this by guiding users visually, presenting a high level abstraction for construction and then generating a “correct by construction” implementation of the system components.

Integrated Power and System Management

In this episode of Chalk TalkHD Amelia chats with Shyam Chandra of Lattice Semiconductor about an integrated approach to system and power management that will lighten your design load, improve your overall system design, and probably lower your total cost at the same time.

Three Ways that Allegro TimingVision Environment Speeds Up Timing Closure of High-Speed PCB Interfaces

On advanced high-speed interfaces, timing closure can be an iterative process that can be time-consuming and frustrating. PCB designers need techniques and tools to make the process more efficient, so they can contribute to an overall faster time to market for the design. This article discusses three ways that the new Cadence Allegro TimingVision Environment speeds up timing closure of high-speed PCB interfaces.

Allegro PCB Editor Timing Environment

Allegro PCB Editor timing environment provides a new level of high-speed routing capability to the engineering desktop resulting in up to 60% reduction in route time. Check out the blog post followed by a short video to learn how Timing Vision in action along with AiPT and AiDT make quick qork of a complex DDR interface.

Building a Custom Verification GUI with System Console

Want to know how to easily create GUI dashboards to interact with your design? Watch this new demo to learn how to: Add run-time visibility into your FPGA systems, access available run-time information using Tcl, a flexible command language, create your own custom verification tool using graphical elements such as buttons, dials, and graphs and develop solutions ranging from simple scripts to sophisticated GUI applications

Generating Panoramic Views by Stitching Multiple Fisheye Images

This white paper discusses an innovative architecture developed by Altera and Manipal Dot Net to generate panoramic views by stitching multiple fisheye images on an FPGA. This architecture provides a complete view of a vehicle’s surroundings to the driver and makes it easier to control and navigate the vehicle.s.

Boosting System Performance with External Memory Solutions

Over 70% of designs on Altera® FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of building external memory solutions with Altera FPGAs, including application needs, memory capabilities of Altera FPGAs, and device and IP selection. Also discussed is the modular style of the memory components, comprised of Altera’s controller and PHY offerings with circuit and calibration features.

7 Series FPGA Transceiver RX Margin Analysis

Many designers either don’t have the equipment to debug an FPGA serial link or when they do, they don’t get much information by physically probing traces on the board. Using PCI-Express as an example, this demonstration will show how to perform system margin analysis during live signal transmission without interrupting data flow.


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