Search On Demand

 
 
 
 

Recommended Reading

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

How to automatically replace LEF abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

Troy Scott, Product Marketing Manager, and Peter Zhang, R&D Engineer, explain RTL debug features available in ProtoCompiler.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Solving Today's Interface Challenges with Ultra-Low Density FPGA Bridging Solutions

Today’s embedded system designers face an unprecedented challenge from an I/O perspective. As system complexity rises, they are increasingly asked to address a multitude of potential I/O options. These options can range from interfacing one industry bus to another, to connecting new and higher performance sensors with mature application processors. Moreover, this problem is pervasive across all markets from high volume consumer applications to the latest industrial, scientific and medical systems.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

OpenCL on FPGAs for GPU Programmers

In this white paper, Acceleware introduces parallel programming targeting Altera® FPGAs using the OpenCL™ framework to graphics processing unit (GPU) programmers. This white paper provides a brief overview of OpenCL, discusses the Altera FPGA architecture and its benefits, and explains how OpenCL kernels are executed and optimized on FPGAs versus GPUs.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Industry’s 1st Single Chip 400GE Solution

Watch a demonstration of the industry’s first single chip solution for 400G applications, featuring the 20 nm Virtex® UltraScale™ device interfacing to Sumitomo Electric CFP4 optical modules and 10 km of optical fiber.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

chalk talks

IP and Process Solutions for Energy-efficient PMICs

In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Maximize Design Productivity With PCIe/104 FPGA/Processor

In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

latest papers and content

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

How to automatically replace LEF abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

How to waive DRC results using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Multi-Board Electrical and Thermal Co-Simulation Using PowerDC

Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.

TimingDesigner: Complex Diagrams

This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

How to easily setup Calibre in Virtuoso for multiple cell windows

This video shows how to setup Calibre Interactive to quickly select from multiple cells open in Virtuoso. Previously there was not a convenient way to setup Calibre Interactive when you wanted to run Calibre in different cells that are simultaneously open in the same Cadence session but now the Layout Cell Browser capability in Calibre Interactive provides an easy and convenient way to select from multiple cells open in Virtuoso.

How to Debug Double Patterning results using Calibre RealTime

This video shows how to easily debug Double Patterning results in Calibre RealTime by using the CTO file to assign different highlight colors to the warning and conflict ring results and to the mask1 and mask2 output layers.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

TimingDesigner Simple Diagrams

This video focuses on drawing simple diagrams in the TimingDesigner program. The presentation covers drawing clocks, signals and buses. It then moves on to edge events, which include delays and constraints. Lastly it covers edge events and the Parameter spreadsheet where it looks at variables, functions, and shows an example of a diagram of a Sharc DSP processor.

« Previous123456...60Next »

New To On Demand?

Registered users can access hundreds of whitepapers, demos, videos, webcasts and more. Sign up now.

Already a registered user? Log in here to access content.

subscribe to journal on demand weekly newsletter

more on demand

Repeatable Results with Design Preservation

Increasingly, FPGA designs are no longer just the “glue logic” of the past; they are becoming more complex every year, often incorporating challenging IP such as PCI Express® cores. The complex modules in newer designs, even when not changing, can present difficulties when attempting to meet qualityof-result (QoR) requirements. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well.

Vivado IP Integrator - Tech Packet

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design.

Reduce Verification Complexity in Low/Multi-Power Designs

The increasing demand for highly reliable products covers many industries, all process nodes, and almost all design implementations. To satisfy this demand, reliability requirements are growing in all market segments.Accurate and repeatable reliability verification is now a critical capability, both for advanced nodes and for increasingly complex products being produced at established nodes. Read more of this whitepaper to learn how to create an easy-to-use, automated verification solution for low-power and multi-power domain designs.

Virtex-6 FPGA Routing Optimization Design Techniques

With the ever-increasing need for high bandwidth, system designers continue to increase resource utilization when designing with Virtex®-6 devices. This can sometimes lead to routing challenges and congestion that can impact design closure. This white paper provides recommendations to help customers mitigate routing challenges in their Virtex-6 FPGA designs.

Power Reduction in Next-Generation UltraScale Architecture

Designed to scale from 20 nm planar technology through 16 nm FinFET and beyond, Xilinx UltraScale™ devices equip an already-successful architectural platform with numerous innovative power reduction techniques. This white paper explores the challenges of managing power efficiently, reducing device power requirements, and innovating new power solutions at the speed of Moore's law.

Accelerating DSP Designs with the Total 28-nm DSP Portfolio

Implementing DSP datapaths with different performance, precision, IP, and development flows is challenging and labor intensive. As more and more high-performance DSP datapaths are implemented on FPGAs, Altera has developed a complete DSP solutions portfolio at 28 nm to address these challenges and speed up the design cycle for FPGA-based applications. This white paper discusses the different components of this portfolio and how they come together to accelerate the implementation of a DSP design.

STMicro Shortens Turnaround Time with Cadence's Mixed-Signal Solutions

STMicroelectronics relies on mixed-signal solutions for its Smart Power Technologies. As Livio Frantantonio explains in this video, STMicro needed to increase productivity and quality of results while shortening its turnaround times. The company found its answer in Cadence's mixed-signal solutions, including Virtuoso® Mixed-Signal Flow. Watch this video to learn how STMicro benefited from using the Cadence Unified Mixed-Signal Methodology.

Hardware Programmability

Learn how FPGAs allow you to customize for your specific needs while enabling you to protect your differentiation in the marketplace.

Next-Generation Packaging for CRM Applications

With smaller electronics, more options can be fit into the package, allowing for features such as RF transceivers for wireless communication, advanced sensors to optimally time pacing and defibrillation shocks and backup systems in case the main system fails. While integrated circuits (ICs) have taken advantage of advances in dense packaging, such as die stacking, in most cases the discrete components remain unchanged. Market pressures are now forcing improvements in the current discrete packaging.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.

Streamline Your Video Processing Apps with Design Examples

Wouldn’t it be great if you could develop your video processing applications faster? You can with a complete suite of ready-to-use video processing functions. These functions are ready to be dropped into your design and connected through open Avalon® Streaming interfaces. Watch this 5-minute video for a demo that shows you a low-cost touch screen-based development kit running two design examples based on these functions.

MachXO2 Infomercial

This video spoof is on the lighter side of Lattice. If you haven’t seen this MachXO2 video yet, check it out. You might even chuckle a bit or at least learn a new way to keep warm and toasty in the lab.

Introducing the User-Customizable ARM-Based SoC FPGA

Learn how to reduce system power, system cost, and board size while increasing performance and flexibility. Altera’s ARM-based SoC FPGAs combine the performance benefits and power and cost savings of hard logic, with the flexibility and time-to-market benefits of programmable logic – all in a single device.

Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesday video, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

Enabling High-Precision DSP Applications with the FPGA Industry’s First Variable-Precision Architecture

The silicon DSP architecture of the FPGA can make a big difference when implementing complex signal-processing algorithms. Altera’s Stratix V FPGAs, with the variable-precision DSP block architecture, are the only programmable devices that efficiently support many different precision levels, including floating-point implementations. Also, with a 64-bit cascade bus and accumulator, the designer does not have to sacrifice precision when the algorithm implementation requires multiple DSP blocks.


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register