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Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

Leveraging MIPI D-PHY-based Peripherals in Embedded Designs

Embedded systems designers face an ongoing dilemma. On the one hand they need to drive down systems costs. On the other they cannot exploit manufacturing economies of scale because their systems are targeted at relatively narrow, low volume applications. While high volume consumer markets offer components capable of performing similar tasks at much lower cost, embedded designers are restricted from taking advantage of those components by their systems’ reliance on highly specialized, legacy interfaces optimized for the embedded environment.

A Significant Technology Advancement in High-Speed Link Modeling and Simulation

This white paper describes how Altera's jitter/noise eye (JNEye) link analysis tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the requirements for accuracy and advanced simulation and modeling techniques.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Using Low Cost, Non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Accelerating Open Source Security Using OpenCL & Altera FPGAs

Today's FPGAs offer interesting potential for accelerating performance- and power-critical operations such as security algorithms. In this episode of Chalk Talk, Amelia Dalton chats with Ryan Kenny of Altera about using FPGAs to accelerate open source security algorithms written in OpenCL.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

It's an Analog World After All

It's an analog world out there. And, while most microcontrollers offer terrific features in the digital and software domain, Microchip has a new family of MCUs with Intelligent Analog capabilities that can make a huge difference in connecting your design to the real world. In this episode of Chalk Talk, Amelia Dalton talks to Alexis Alcott of Microchip about harnessing the power of Intelligent Analog in MCU design.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

chalk talks

FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit

In this episode of Chalk TalkHD Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.

How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series)

In part 1 of this 3-part series, we talked about how you can save 75% on your next mixed-signal chip design - which was great, but we think we can do better than that. In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity even more. In this second epsiode of our 3-part Chalk TalkHD series, Amelia and Reid tell you how to save up to 99% on your design.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

latest papers and content

Simulation Key to Automotive Challenges

This paper describes a new virtual prototyping environment that allows system integration to begin before physical hardware can be made available, a valuable commodity in today’s complex automotive system design process.  This new technology gives designers powerful tools for managing mechanics, electronics, software, and controls in one system with the capability to integrate the significant intersections between them.

Simulating Vector Controlled Induction Motors Using Space Vector Modulation

This paper illustrates the development of a comprehensive vector-controlled induction motor drive system using a virtual prototyping environment for the development/simulation of all designs. Motion control system development poses many challenges for conventional simulation tools. Not only are these systems extremely complex, they traverse both technology (domain) boundaries, as well as analog/digital boundaries. Conventional simulation tools cannot adequately deal with these diverse modeling requirements.

Allegro FPGA System Planner

The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin count FPGAs on the PCB board. By replacing manual error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment.

Aldec Active HDL Datasheet

Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager. Active-HDL has interfaces to over 80 leading EDA tools, making it the most powerful environment. Check out the top features and product configurations to see if Active-HDL is right for you.

Formal VIP for 100% Accurate Designs

In this week's Whiteboard Wednesdays video, Tom Hackett discusses formal verification IP (VIP), how it supports formal analysis, and how design engineers can leverage formal VIP to ensure their designs are 100% correct. Learn more about Cadence IP at http://ip.cadence.com.

How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design. Learn more about Cadence IP at http://ip.cadence.com.

Reduce Project Schedules and Increase Quality using Model Driven Development for Design, Verification, and Test

This paper shows how Model Driven Development can address common challenges in the system design, verification & testing of complex systems. Project success requires that hardware, software, and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components, which often proves to be costly in terms of time, money, and engineering resources. This paper covers such solutions that reduce project schedule while improving product release quality.

Modernizing System Development

Allowing disconnected development and waiting until the latest program stages to perform systems integration and connect all the pieces is a high risk situation, yet one all too common in today’s product realization process. Bringing domain expertise together as appropriate throughout a project’s development process is imperative for project success.  This paper explores a more modern approach to system development built on a Model Driven Development (MDD) approach.

Successfully Designing FPGA-Based Systems

One key challenge in successfully designing FPGA-based systems is choosing the right FPGA for the design needs, and maximizing the use of FPGA resources. In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.

Addressing the “Power-Aware” Challenges of Memory Interface Designs

One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing high-speed memory interfaces. This paper assesses how modern tools can be used to address power-aware SI challenges with I/O modeling, interconnect modeling, simulation, and analysis.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis Tech Packet

How to Effectively Manage Timing of FPGA Design Flow

When combined with advances in FPGA technologies for interface design efforts, EMA TimingDesigner can simplify design issues and provide advanced accurate control of virtually any interface. From simple SRAM interface protocols to high-speed source synchronous interface protocols, TimingDesigner allows designers to identify potential timing problems early in the design process and thereby providing the greatest opportunity to get the timing right the first time. This white paper will show you how to effectively integrate TimingDesigner with Xilinx and Altera Development Systems.

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Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency

The programmable imperative—the critical need to achieve more with less, to reduce risks wherever possible, and to quickly create differentiated products using programmable hardware design platforms—is driving the search for FPGA-based solutions that provide the capacity, lower power, and higher bandwidth with which users can create the system-level functionality currently delivered by ASICs and ASSPs. Download this whitepaper to learn more.

Xilinx Redefines Power, Performance, and Design Productivity with Three New 28 nm FPGA Families:Virtex-7, Kintex-7, and Artix-7 Devices

Three new Xilinx product families leverage the unprecedented power, performance, and capacity enabled by TSMC's 28 nm high-k metal gate (HKMG), high performance,low power (HPL) process technology and the unparalleled scalability afforded by the FPGA industry's first unified silicon architecture to provide a comprehensive platform base for next-generation systems. Watch this webcast to learn more.

Implementation of 9x9 Multiplications, Wide-Multiplier, and Extended Addition Using IGLOO2/SmartFustion2 Mathblock App Note

This application note highlights design guidelines and different implementation methods to achieve better performance results while implementing wide-multipliers, 9-bit×9-bit multiplications, and extended addition with the IGLOO2/SmartFusion2 mathblock (MACC). The 9-bit×9-bit multiplications, wide-multiplier, and extended addition are ideal for applications with high-performance and computationally intensive signal processing operations. Some of them are finite impulse response (FIR) filtering, fast fourier transforms (FFTs), and digital up/down conversion.

Strategic Considerations for Emerging SoC FPGAs (REVISED)

Semiconductor devices that integrate FPGA fabric, hardened CPU subsystems, and other hardened IP—SoC FPGAs—have reached a tipping point that will lead to their broad proliferation in the next decade, therefore offering many options for system designers. These SoC FPGAs complement the decade-long availability of soft-core CPUs and other soft IP for building systems on FPGAs. This white paper describes the emergence of system on a chip (SoC) FPGAs, the drivers behind that emergence, and strategic considerations for executive management and system designers when choosing these devices.

EasyPath-6 Technology: Fast, Simple, Risk-Free FPGA Cost Reduction

Virtex®-6 FPGAs are the industry's leading platform for designing complex systems in the fields of wired and wireless communication, storage, computing, instrumentation, automotive, industrial, and medical. Virtex-6 FPGAs not only deliver the most attractive set of features and functionality and the fastest time to market advantage, they are also paired with EasyPath™-6 technology, the fastest path to cost reduction.

Zynq-7000 All Programmable SoCs Deliver Proven Productivity

Xilinx offers a robust and extensive infrastructure that enables Zynq®-7000 SoC users to be more productive and get their designs to market quickly. The Vivado®-HLS or high level synthesis tool allows designers to make architectural tradeoffs rapidly and develop highly optimized systems in the Zynq-7000 device. The Zynq-7000 platform also includes support for today’s most popular software design environments and Xilinx offers a proven portfolio of IP, design kits and reference designs.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Simplifying Industrial Ethernet Design

In this episode of Chalk TalkHD Amelia chats with Suhel Dhanani of Altera about the who, what, and how of industrial ethernet design.

Supporting Digital Television Trends with Next-Generation FPGAs

What do the following items have in common: iPhones, Avatar 3D, digital SLR cameras, and LCD digital televisions? They are all evidence that consumers strongly prefer products with “stunning” visuals. This white paper shows how these trends towards new features and faster introduction rates of new models are fueling increased FPGA use within high-definition television electronics. The digital television market is growing, with the number of LCD-based digital televisions growing at 22% CAGR.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Xilinx DSP Targeted Design Platforms Deliver Performance, Price, Power, and Productivity

Digital signal processing (DSP) design starts have surpassed every other segment of the processing arena. Consequently, the demand for differentiated value in every aspect of DSP design has never been higher, increasing pressure on the teams tasked to build winning designs in record time. Xilinx conceived the Targeted Design Platform to address this challenge—the necessity to do more with less, to remove risk wherever possible, and to differentiate in order to excel.

SmartFusion Intelligent Mixed Signal FPGAs in Motor Control Applications

This video provides an exploration of Motor Control applications using Actel's SmartFusion™ intelligent mixed signal flash FPGAs for field-oriented closed-loop motor control for brushless DC (PMSM) motors, with a closer look at your challenges and a look into the Actel motor control development kit currently in development.

Repeatable Results with Design Preservation

Increasingly, FPGA designs are no longer just the “glue logic” of the past; they are becoming more complex every year, often incorporating challenging IP such as PCI Express® cores. The complex modules in newer designs, even when not changing, can present difficulties when attempting to meet qualityof-result (QoR) requirements. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well.

Optimize Power and Cost with Altera’s Diversified 28nm Device Portfolio (REVISED)

Altera’s 28-nm devices provide a diversified product portfolio tailored to support a broad spectrum of applications, ranging from low cost and power, to high-end applications. This white paper describes the power and cost advantages of Altera’s Stratix® V, Cyclone® V, Arria® V, and HardCopy® V devices.

SDNet Overview with VP Nick Possley

Xilinx Vice President Nick Possley discusses how the new Software Defined Specification Environment for Networking (SDNet) is enabling 'Softly' Defined Networks, what benefits it's bringing to system architects and why it's considered revolutionary.

What Is VIP?

Watch this week's episode to hear Tom Hackett, product director at Cadence, talk about the important role that VIP plays in the verification process. Tom details how VIP provides known good designs and stress testing for all interfaces and memory components, helping you to develop bug-free chips.

Arria V FPGA Sneak Peek: Transceiver Operation at 6.325 Gbps and 10.3125 Gbps

When you want it all, Arria® V devices provide the balance of cost and performance while delivering the lowest total power. Watch this exciting hardware demonstration of the Arria V FPGA's transceiver running at 6.375 Gbps and 10.3125 Gbps.

Hardware Accelerated H.264 Video Encoding using VAAPI on the Intel® Atom™ Processor E6xx Series

The Intel® Atom™ Processor E6xx Series for the embedded devices market includes the POWERVR* VXE core that provides video encoding capabilities, allowing to encode high definition video streams in the highly compressed H.264 format with a very low main CPU utilization, releasing the general purpose processor for other parallel workloads. This processor feature is available to application developers by means of the open Video Acceleration API (VAAPI [1]). This paper explains how the VAAPI can be applied to a real time video encoding task, explaining the VAAPI function calls flow, and the corresponding parameters.


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