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Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.

Artix-7 FPGA Transceiver: The Industry's Most Capable Transceiver in a Low-End Device

In this video you’ll see the FPGA industry’s only low end transceiver solution—the Artix-7 FPGA transceiver—that provides auto-adaptive equalization, 2D Eye Scan, and IBIS-AMI simulation models to simplify high speed serial design for cost-sensitive applications.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources. Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

Building a New Type of IP Factory

Reliable IP blocks are essential to the success of most modern SoC and custom IC designs. But finding a reliable, reputable source of verified IP can be challenging. In this episode of Chalk Talk, Amelia Dalton talks to Kevin Yee (Cadence Design Systems) about Cadence's substantial IP offerings

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Using Low Cost, non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

Battery Management Solutions

Designing battery-powered systems can be challenging. In addition to power and form-factor considerations, today's batteries require sophisticated charging and monitoring for maximum safety, life, and performance. In this episode of Chalk Talk, Amelia Dalton chats with Richard DelRossi of Texas Instruments about battery management solutions that can dramatically simplify your next battery-powered design while adding important monitoring capabilities to your device.

SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User’s Guide

This demo design shows SmartFusion®2 SoC FPGA device capabilities for code shadowing from serial peripheral interface (SPI) flash memory to single data rate (SDR) synchronous dynamic random access memory (SDRAM) and executing the code from SDR SDRAM. Code shadowing is a booting method that is used to execute an image from external faster volatile memories (DRAM) and is the process of copying the code from nonvolatile memory to volatile memory for execution. In performance critical applications, execution speed can be improved by code shadowing where code is copied to higher throughput RAM for faster execution.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

It’s Easy to Protect Your Embedded System from Theft

If you have invested years and millions of dollars in the design of an embedded system (and in the creation of the Intellectual Property, or IP, that goes along with the design) it can be of critical importance to protect that system from unauthorized duplication or theft. After all, it’s much easier to steal something as complex as a multi-million gate FPGA design than to create, debug, and test it. The protection of an embedded system that uses FPGAs, is particularly relevant since FPGAs have become the platforms of choice for innovation.

How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series)

In part 1 of this 3-part series, we talked about how you can save 75% on your next mixed-signal chip design - which was great, but we think we can do better than that. In this episode of Chalk TalkHD Amelia chats with Reid Wender of Triad Semiconductor about how you can dramatically reduce design costs and complexity even more. In this second epsiode of our 3-part Chalk TalkHD series, Amelia and Reid tell you how to save up to 99% on your design.

Introducing Digitally Enhanced Power Analog

Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

chalk talks

Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.

Introducing Digitally Enhanced Power Analog

Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

Smartphone and Tablet Accessory Design

In this episode of Chalk TalkHD Amelia Dalton talks to David Flowers from Microchip about creating tablet and smartphone accessories - and how it just may be easier than you think...

Advanced Smart Display Solutions

In today's mobile designs, displays are one of the most important components in differentiating your product. As a result, more people are designing high-resolution displays into mobile devices. But, adding a high-res display to your design can be a complex task. In this episode of Chalk Talk, Amelia chats with Pavel Klinger (GLOBALFOUNDRIES) about GLOBALFOUNDRIES' solutions for the new generation of high-resolution smartphone displays.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

latest papers and content

How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources. Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

Artix-7 FPGA Transceiver: The Industry's Most Capable Transceiver in a Low-End Device

In this video you’ll see the FPGA industry’s only low end transceiver solution—the Artix-7 FPGA transceiver—that provides auto-adaptive equalization, 2D Eye Scan, and IBIS-AMI simulation models to simplify high speed serial design for cost-sensitive applications.

Xilinx Broadest Cost Effective All Programmable Low-end Portfolio

This generation of all programmable, cost-sensitive applications has reached new levels of sophistication and diversity of requirements. Low cost systems in the consumer, automotive, industrial, medical, and communications space may need a programmable logic device with high serial bandwidth, or for advanced processing, or may simply need bridging functionality and little else. Commonly termed the “low-end” market due to the devices’ relatively low cost and density, these platforms provide varying levels of system integration, performance, and power. They may perform critical tasks such as video analytics or packet processing, or simply expand a system’s I/O connectivity to peripheral devices.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Using Low Cost, non-volatile PLDs in System Applications

The system market is comprised of applications in telecom infrastructure, computing, high end industrial and high end medical. Power supply sequencing, voltage and current monitoring, bus bridging, voltage level translation, interface control, and temperature measurement are typical board functions found in these applications. System designers are faced with continual pressure to meet their development schedules, and need to implement designs with minimal effort and risk while maintaining maximum flexibility. By using a programmable-based approach instead of several discrete devices or Application Specific Standard Products (ASSPs), designers can accelerate their time-to- market, address system cost and space reduction, and ensure a high level of product differentiation.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs. These challenges can easily be overcome with the use of FPGAs (field programmable gate arrays), which over the past 10 years have seen a significant reduction in cost and power consumption, making them ideal for a wide range of high- volume, low-cost applications including mobile.

Security Aspects of Lattice Semiconductor iCE40 Mobile FPGA Devices

Product piracy is of strong concern to major companies around the world. R&D costs are very high for leading companies. Therefore, companies plan to recoup these R&D costs by sale of their proprietary products. If pirates are able to steal or copy the final design, or countermand the security systems of these proprietary products, the market will become flooded with low cost alternatives. As a final consequence, major companies will find themselves unable to recover their high development costs, and will lose valuable profits.

Vivado IP Integrator - Tech Packet

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include ARM AMBA 4, ARM AMBA 5, OCP, DDR, LPDDR, LPDDR3, LPDDR4, Wide I/O, Wide I/O2, DRAM, eMMC, eMMC5, UFS, CSI-3, SoundWire, USB, PCIe, and SSIC.

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more on demand

Infotainment Companion Chip Development Platform Demo

Davor Kovacec, CEO of Xylon, demonstrates a flexible host-interfacing platform. Co-developed with Xilinx Premiere Alliance Member Xylon, the Spartan-6 FPGA Infotainment Companion Chip Targeted Design Platform enables flexible interfacing on a rapid development cycle.

Medical Imaging Implementation Using FPGAs

Medical imaging equipment is taking on an increasingly critical role in healthcare as the industry strives to lower patient costs and achieve earlier disease prediction using noninvasive means. To provide the functionality needed to meet these industry goals, equipment developers are turning to programmable logic devices such as Altera’s FPGAs.

Building a Custom Verification GUI with System Console

Want to know how to easily create GUI dashboards to interact with your design? Watch this new demo to learn how to: Add run-time visibility into your FPGA systems, access available run-time information using Tcl, a flexible command language, create your own custom verification tool using graphical elements such as buttons, dials, and graphs and develop solutions ranging from simple scripts to sophisticated GUI applications

Conquer FPGA Design Complexity with System-Level Integration

Having trouble meeting deadlines? Is your FPGA design growing but when you look around, your team is still the same size, or worse, smaller? Do you wish reusing someone else’s design would work seamlessly? Watch this webcast to see how you can increase your FPGA design productivity. Find out how to quickly develop large, complex systems by integrating other smaller complete systems and intellectual property (IP).

Lower Power and Boost System Bandwidth on 28nm FPGAs

It’s a challenging balancing act to meet growing bandwidth demands without increasing cost or power consumption. And it’s probably a challenge you know well if you’re designing high-end systems in areas such as communications, broadcast, military, and computer/storage. Achieve the right balance with Altera’s Stratix® V FPGAs, which deliver breakthrough bandwidth, reduced cost, and the lowest total power.

Overcome Design Challenges with an Innovative IP Scalability, Integration, and Delivery Model

Intellectual property (IP) is a key component in system designs for many different end markets. This white paper explores how Altera and partner IP solutions can provide the differentiation you need for your next-generation applications. This white paper examines the feasibility of developing IP in-house or buying from a third party, and also presents Altera's innovative IP scalability, integration, and delivery model. With this model, Altera not only simplifies the process of acquiring, evaluating, testing, and integrating IP into your design, but also mitigates the risks of using third-party IP.

Security Aspects of Lattice Semiconductor iCE40 Mobile FPGA Devices

Product piracy is of strong concern to major companies around the world. R&D costs are very high for leading companies. Therefore, companies plan to recoup these R&D costs by sale of their proprietary products. If pirates are able to steal or copy the final design, or countermand the security systems of these proprietary products, the market will become flooded with low cost alternatives. As a final consequence, major companies will find themselves unable to recover their high development costs, and will lose valuable profits.

Designing a Power Distribution Network for High-End FPGAs

Progress to smaller FPGA process geometries has led to shrinking noise margins and lower voltages. These changes mandate higher currents, tighter voltage tolerances, and management of multiple power rails. Every board designer has to learn how to deliver clean power to the FPGA, as making the wrong choice can severely reduce functionality and performance.

Accelerate Your Video Format Conversion Using 1080p Framework

In today’s digital studio, video format conversion is challenging and time-consuming, yet necessary. Learn about an easy method for up-conversion, down-conversion, and cross-conversion of SD and HD video streams. Watch this 8-minute video to: See how a 1080p format conversion reference design provides a flexible, customizable template for fast conversion, right out of the box. See broadcast-quality motion adaptive deinterlacing and multi-tap polyphase scaling running on Altera's Audio Video Development Kit. Find out how to get a jump start developing broadcast systems ranging from switchers to multi-view displays.

Firm Error Immunity in Flash FPGAs

Radiation effects are not isolated to space electronics only, but they affect all type of electronics whether they are automotive, industrial or military and avionics. What differentiates them is the type of radiation. This webcast shows how FPGA’s interact with them and why Actel FPGAs are the best solution to mitigate these effects.

10 Ways to Effectively Debug your FPGA Design

Today’s FPGAs implement the equivalent of millions of ASIC gates and continue to grow in size and complexity. With the increasing amount of time designers are spending debugging and diagnosing the design, there is a need both for better ways to find errors early and en masse, and for smarter techniques to isolate errors and apply incremental fixes. The newest generation of the Synplify Premier synthesis tool addresses these needs by supporting early design checks and hierarchical design approaches.

New MIPI Interfaces: Winners or Losers?

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a deeper look at the MIPI protocols that are the leading choice for certain mobile interfaces. Even though MIPI protocols are a top choice, however, they are being challenged by mobile versions of PCI Express and USB. Given this landscape, what does the future look like for MIPI and its challengers? Watch this short video to find out!

Broadcom Uses Palladium XP to Validate New Architecture of Mobile SoC

Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence(r) Palladium(r) XP to validate a new architecture for a complex mobile SoC for mobile platform devices.

Zynq-7000 All Programmable SoCs Deliver Unmatched Performance and Power

Xilinx Zynq®-7000 All Programmable SoC devices fuse a fast processor system (PS) based on two 1GHz ARM Cortex™-A9 MPCore processors with the industry’s fastest and most advanced 28nm programmable logic (PL) fabric, a large on-chip memory, multiple high-speed serial transceivers, numerous hardened peripheral IP cores including DDR and Flash memory controllers, and an on-chip analog-processing block that incorporates two 1Msamples/sec A/D converters. Zynq-7000 devices offer unmatched performance with low operating power.

Developing Safety Critical Applications that Meet IEC 61508 Standards

With the rapidly growing requirements for advanced safety and security in embedded network connected devices, not only will traditionally safety conscious designs need to implement advanced capabilities, but even traditionally mainstream industrial applications are seeing similar requirements emerging. SmartFusion2 devices are clearly the best-in-class solution for implementing safety critical, high-reliability designs. In addition, the advanced security features available in SmartFusion2 devices help create the secure life cycle on which high-reliability implementations ultimately depend.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

8 Reasons to Use FPGAs in IEC 61508 Functional Safety Applications

FPGAs are increasingly replacing electronic components used for industrial applications, thus international standards like the IEC 61508 have to support these evolving technology trends if they want to keep their relevance. This white paper gives developers eight simple reasons why FPGAs should be chosen in their IEC 61508 functional safety project versus standard microcontrollers or DSPs.

Accelerate Your Video Processing Application Using Reference Designs

Wouldn´t you like an integrated solution that makes developing broadcast infrastructure equipment easier and faster? Watch this new 9-minute video to learn about two development kits and reference designs that do just this.


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