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Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

OpenCL on FPGAs for GPU Programmers

In this white paper, Acceleware introduces parallel programming targeting Altera® FPGAs using the OpenCL™ framework to graphics processing unit (GPU) programmers. This white paper provides a brief overview of OpenCL, discusses the Altera FPGA architecture and its benefits, and explains how OpenCL kernels are executed and optimized on FPGAs versus GPUs.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User’s Guide

This demo design shows SmartFusion®2 SoC FPGA device capabilities for code shadowing from serial peripheral interface (SPI) flash memory to single data rate (SDR) synchronous dynamic random access memory (SDRAM) and executing the code from SDR SDRAM. Code shadowing is a booting method that is used to execute an image from external faster volatile memories (DRAM) and is the process of copying the code from nonvolatile memory to volatile memory for execution. In performance critical applications, execution speed can be improved by code shadowing where code is copied to higher throughput RAM for faster execution.

It's the Software, Silly! - Success with FPGA-based Prototyping

Software is becoming a larger and larger part of our system-on-chip (SoC) designs. It is critical that we be able to begin developing and debugging software as early as possible in the design cycle. But, the hardware part of today's complex designs takes months to stabilize. In this episode of Chalk Talk, Amelia Dalton talks with Juergen Jaeger of Cadence about the tight relationship between software and emulation and how you can achieve success in your SoC design with a comprehensive emulation strategy.

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.

New Approaches to Hardware Acceleration Using Ultra Low Density FPGAs

Ask system designers to list the problems they face – it doesn’t matter whether they’re building mobile consumer, automotive, industrial, medical or scientific applications – and inevitably they’ll mention optimizing host processor performance. It’s hardly surprising. The event-driven architecture of these MPUs allows them to multitask and address new priorities as they occur. But as the number of I/O continues to rise, it also places escalating demand on bandwidth. Tasked with managing a wider array of I/O as well as other system-wide command and control functions, today’s host MPUs must remain operational for longer periods of time, thereby consuming precious power and compute resources.

Bridging MIPI Technologies with ULD FPGAs

With mobile-based standards such as MIPI sweeping the design landscape, we will often find ourselves in the situation of needing to bridge between legacy interfaces and newer MIPI-based ones. In this episode of Chalk Talk, Amelia Dalton talks to Ted Marena of Lattice Semiconductor about using ultra-low-density FPGAs in mobile devices to enable us to get our other interfaces to play nicely with MIPI - with form-factors and power efficiency that are right at home in mobile devices.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

System Design with Advance FPGA Timing Models

Advanced FPGAs are difficult to characterized due to their advanced process nodes, which delays the availability of final timing models until silicon characterization is completed. This paper describes the timing models available for end-user FPGA design, in advance of production FPGAs. This paper explains the development cycle of FPGAs, along with the timing models available at each stage. This paper also describes the best practices that you can use at each stage of the timing model.

World's Smallest FPGAs Solve 4 Big Problems

In this episode of Chalk Talk, Amelia chats with Gordon Hands (Lattice Semiconductor) about some awesomely tiny FPGAs that bring the power of programmable logic into devices like cell phones, tablets, and other power and form factor sensitive applications.

15Gb/s HMC Interface for UltraScale Devices

Watch a demonstration of the industry's first 15Gb/s HMC interface by Xilinx and Pico Computing at the International Supercomputing Conference.

Accelerating System Bandwidth with FPGAs and Hybrid Memory Cube

Move over DDR, the Hybrid Memory Cube (HMC) is here! But, from a design perspective, care and feeding of the amazing HMC can be a lot more demanding than DDR. In this episode of Chalk Talk, Amelia Dalton and Manish Deo of Altera explain how powerful FPGAs can help you tame the HMC in your next design.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Infineon's 8th Generation of RF Transistors Maximize Receiver Sensitivity and Range

If you're designing systems that use the latest WiFi standards, you know that a great RF transistor with high gain and low noise is key to good performance. In this episode of Chalk Talk, Amelia Dalton talks with Andrew Nelson of Infineon about the latest in high-performance RF transistors - Infineon's new 8th generation.

chalk talks

Cadence Tempus Timing Signoff Solution

Achieving timing closure for signoff can be a daunting challenge in today's complex designs. Meeting timing under all conditions - with the certainty required for signoff - is a complex and demanding task. In this episode of Chalk Talk, Amelia Dalton talks to Ruben Molina of Cadence Design Systems about the special challenges of signoff timing closure, and Cadence's new Tempus timing analysis tool.

GLOBALFOUNDRIES RFCMOS Solutions and Catena WiFi Solutions

In this episode of Chalk TalkHD Amelia Dalton chats with Fayyaz Singaporewala (GLOBALFOUNDRIES) and Mats Carlsson (Catena) about how to get that scary RF portion of your next design done in a snap.

Intel Atom™ Processor with built-in Altera Arria® FPGA

In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.

Spartan-6 FPGAs in Video Designs

In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Digital Predistortion for Base Station Power Amplifiers

In this episode of our new Chalk TalkHD series, Amelia Dalton talks to Todd Nelson from Linear Technology about how digital predistortion (DPD) can be used to save millions of dollars worth of power in base station designs. DPD is simple to apply, and has a dramatic impact on the power amplifier - the most power-hungry part of modern base stations. In this Chalk TalkHD you'll hear how DPD works and how you can apply it to your next design.

Introducing SmartFusion2 FPGAs

In this episode of Chalk TalkHD Amelia Dalton chats with Wendy Lockhart of Microsemi about Microsemi's biggest FPGA announcement this year - SmartFusion2. This new family can do things we never expected from Microsemi's non-volatile FPGAs. Watch this Chalk Talk to learn what it's all about.

Getting Started Using Kintex-7 FPGAs for DSP

In this episode of Chalk TalkHD Amelia chats with Tom Hill of Xilinx about their new Kintex-7 DSP development kits that will finally get you onto the rocket-coaster of FPGA-powered DSP.

latest papers and content

Product Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Injecting Automation into Verification - Assertions

What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

Strategies to Develop Secure and Robust Embedded Devices

Learn a pragmatic approach to configuring a heterogeneous multicore ARM® device built with ARM TrustZone™ technology and trade-offs of various implementations.

Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesday video, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

15Gb/s HMC Interface for UltraScale Devices

Watch a demonstration of the industry's first 15Gb/s HMC interface by Xilinx and Pico Computing at the International Supercomputing Conference.

Xilinx and Open-Silicon HMC Memory Solution

Watch a demonstration of the industry's first available 12.5 Gb/s Hybrid Memory Cube (HMC) interface using the Xilinx Virtex®-7 FPGA. See how this solution provides superior memory bandwidth for your application using HMC technology, Virtex-7 FPGA, and Open-Silicon IP.

Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays video, Moshik Rubin discusses the history of the PCI Express standard. Moshik starts with PCIe Gen1, which originated in 2002, and walks through the doubling of throughput offered by each new generation, ending with PCIe Gen4.

Selecting an Operating System (OS) for Embedded Application

It seems these days, just about every embedded system has some type of operating system. And there are more options today as to which OS to choose. Is open source your best choice? What about a free RTOS? In this paper, learn the pros and cons of the many OS options available today and how to select the right OS for your next embedded project.

Navigating the FDA Approval Process for Your Software Based Medical Device

Understand how to get your product to market within product launch schedules. Review challenges companies face as they seek FDA approval and review guidance and resources to assist with successfully navigating the approval process. Learn about a number of important areas including premarket submissions, documentation, verification and validation (V&V), user experience and human factors design, and cybersecurity.  Presented by Steve Robertson with Mentor Graphics Embedded Software.  

Using USB IP Controllers in Today's Devices

In this week's Whiteboard Wednesdays video, Jacek Duda follows up on his earlier video focused on USB performance and now takes a closer look at USB IP controllers and their roles in today's devices.

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Xilinx Redefines Power, Performance, and Design Productivity with Three New 28 nm FPGA Families:Virtex-7, Kintex-7, and Artix-7 Devices

Three new Xilinx product families leverage the unprecedented power, performance, and capacity enabled by TSMC's 28 nm high-k metal gate (HKMG), high performance,low power (HPL) process technology and the unparalleled scalability afforded by the FPGA industry's first unified silicon architecture to provide a comprehensive platform base for next-generation systems. Watch this webcast to learn more.

Put 1080p High-Definition Analytics into Your IP Camera

Advanced analytics is replacing simple motion detection in surveillance cameras. See how you can get 1080p high-definition (HD) analytics in your IP camera with a single-chip video analytics solution.

Accelerate Your Video Format Conversion Using 1080p Framework

In today’s digital studio, video format conversion is challenging and time-consuming, yet necessary. Learn about an easy method for up-conversion, down-conversion, and cross-conversion of SD and HD video streams. Watch this 8-minute video to: See how a 1080p format conversion reference design provides a flexible, customizable template for fast conversion, right out of the box. See broadcast-quality motion adaptive deinterlacing and multi-tap polyphase scaling running on Altera's Audio Video Development Kit. Find out how to get a jump start developing broadcast systems ranging from switchers to multi-view displays.

28Gbps Serial Transceiver Technology (HD 1920x1080)

Join Dr. Howard Johnson and Jack Carrel, Senior Staff Application Engineer from Xilinx as they review the new Virtex-7 HT FPGA family from Xilinx.

Xilinx at NAB 2014 | OmniTek OZ 745

Michael Hodson, President of OmniTek, demonstrates their Scalable Video Pipeline and the Real-time Video Engine OZ 745 development platform which is based on the Zynq® 7045 AP SoC.

Developing Medical Device Software Confirming with IEC 62304 Standard

The IEC 62304 standard for medical device software complies with requirements in the European Union and the United States. Learn about this standard, how to manage risks and establish best practices in the software life cycle to support certification and audit to meet the requirements for IEC 62305.  Explore topics that include using software of unknown provenance (SOUP), mitigating risk throughout the life cycle, managing requirements, code quality standards and configuration management.

Enable High-Performance DSP with Variable-Precision DSP Blocks

DSP designs use hundreds or thousands of multipliers as basic building blocks to implement filters, fast Fourier transforms (FFTs), and encoders that digitally process signals. This document highlights the benefits of variable-precision DSP architecture in Altera’s new Arria® V and Cyclone® V FPGAs. Altera's variable precision DSP block allows designers to tailor the precision on a block-by-block basis, thereby saving resources and power while increasing performance.

Xilinx at NAB 2014 | intoPIX Video Transport Solution

Gael Rouvroy, CTO at intoPIX, demonstrates the intoPIX video transport solution that is based on AVB and SMPTE 2022 and runs on Xilinx Kintex®-7 boards.

Designing for Low Power

FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3’s static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs.

Super Low Power MCUs: NanoWatt XLP Technology

In this episode of Chalk TalkHD Amelia chats with Jason Tollefson of Microchip Technology about a radical new line of microcontrollers from Microchip that combine amazing processing capability with almost unbelievably low power consumption.

Platform Manager Overview

Watch this 5-minute video to: See an overview of the Platform Manager product family, learn how Platform Manager reduces cost, improves reliability and lowers risk, find out how easy it is to get started using the PAC-Designer software design tool and view a live demonstration of the Platform Manager development kit operation.

Taking Command of MIPI PHYs

In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means to "take command of MIPI PHYs." This is a first of a three-part series on the topic. Here, Kevin introduces you to D-PHY and its architecture, and how the protocol meets the requirements of mobile devices.

Single-Event Upsets (SEUs) and Medical Devices

Medical devices are not only susceptible to nature’s cosmic rays, but also must operate in radiation environments found in modern medical facilities. As evidence of these effects mounts, designers of medical devices must now also consider SEU susceptibility when choosing the technology that will form the basis for their products. This paper defines what the risks are and explains ways to mitigate and avoid these risks within programmable logic.

Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesday video, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.

Vivado Design Flows Overview v2013.1

Learn about the various use models for the Vivado Design Suite, as well as, the main features of the Interactive Design Environment (IDE) and Tcl-based design flows from synthesis and simulation through implementation. For More Vivado Tutorials please visit: www.xilinx.com/training/vivado

Overcoming Smart Grid Equipment Design Challenges with FPGAs

Smart grid systems offer the engineer significant design challenges as these systems must have longevity, from not only a reliability standpoint but also from the perspectives of performance and functionality. In addition, smart grid products require their designers to keep abreast of the latest standards and make provisions for inevitable upgrades and updates. The Altera® Cyclone® V FPGA and Cyclone® V SoC families provide engineers with technology—silicon, development tools, and intellectual property (IP)—that provide superior reliability, performance, time to market, maintainability, and cost.

10GBASE-KR Electrical Conformance with Virtex®-7 FPGAs

7 series FPGA GTH transceivers have achieved 100% electrical conformance to the 10GBASE-KR standard. In this video you'll see a Virtex®-7 FPGA pass the specification's receiver interference tolerance test over a 24" backplane.

Seven Steps to an Accurate Worst-Case Power Analysis Using Xilinx Power Estimator (XPE)

Power and cooling specifications for an FPGA design have to be determined early in the product’s design cycle, often even before the logic within the FPGA has been designed. An accurate worst-case power analysis early on helps you avoid the pitfalls of overdesigning or underdesigning your product’s power or cooling system


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