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Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Mixed Signal Verification: The Long and Winding Road

Verification of your mixed-signal design can be a nightmare, with clashing disciplines and engineering cultures, and challenging use-case requirements. In this episode of Chalk Talk, Amelia Dalton chats with Steve Carlson of Cadence Design Systems about a comprehensive approach to mixed-signal system verification.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Solution for Heterogeneous Multicore Embedded Systems

Designing software for heterogeneous multicore embedded systems is a daunting challenge. Each of those words "heterogeneous", "Multicore", and "embedded" represents something that can cause a major breakdown in the normal software development flow. In this episode of Chalk Talk, Amelia Dalton chats with Felix Baum of Mentor Graphics about challenges and solutions for heterogeneous multicore embedded design.

How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse

Engineering teams are under more pressure than ever before as SoCs grow more complex and design schedules become increasingly tighter. With its productivity advantages, high-level synthesis (HLS) has long been touted as part of the solution, but its sweet spot has traditionally been limited to datapath-centric blocks. Moreover, design productivity is only one part of the equation. Verification is often an even bigger hurdle. This paper discusses how HLS can be used to improve the design, verification, and reuse of intellectual property (IP). The paper also introduces a new HLS tool that provides excellent power, performance, and area (PPA) results across the digital design space.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Cognitive Layering Technique for Low-Energy, Sensor-Rich Devices

In this week's Whiteboard Wednesdays video, Chris Rowan talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Sigrity PowerSI Tackles SSO Noise: Customer Success Story

AEI Systems needed to perform a worst case SSO analysis to screen their design and verify that defects and deficiencies would be eliminated prior to test, production and delivery. In doing so, they found that Cadence Sigrity PowerSI was the only tool tested that was able to provide the close correlation to the actual measurement needed to validate the RTAX board example. Click to see the process and results AEI Systems saw using Sigrity PowerSI to successfully evaluate worst case SSO noise.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Accelerating Your Analog Output Design

Eventually, most of our designs need to control something in the real world. That means we have to bust out of our safe little digital realm, and drive some analog actuators or something similar. But, building that analog output section from scratch can be a real challenge. In this episode of Chalk Talk, Amelia Dalton talks to Bill Laumeister of Maxim Integrated about the Analog Output Design Accelerator Kit (MAXREFDES24EVSYS), a complete platform for easy evaluation that requires no lab equipment.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Shaving Weeks Off PCB Design Cycle Via Auto-Routing

To keep up with product refresh cycles as well as quality expectations, the Polycom hardware team decided it was time to move to auto-routing of their PCB boards, using tools including OrCAD Capture CIS for schematic design entry and synchronization/validation of parts data, Allegro PCB Designer for constraint-driven design, and Allegro PCB Router for auto-routing.

chalk talks

Hierarchical Design Flows: Design Preservation & Team Design

In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.

Cadence Low Power Solution - RTL to GDSII Low Power Design

Low-power design used to be an afterthought. Today, however, we need to consider power throughout the entire design cycle - from RTL all the way through GDSII. And, we can have significant impact on overall power consumption with optimizations at just about every stage. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence about a holistic approach to low-power design.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family

Your design needs to connect to the Internet of Things (IoT), doesn't it? Connecting your device to the rapidly expanding IoT opens up a wide world of potential new capabilities. In this episode of Chalk Talk, Amelia Dalton chats with Andreas Eieland (Atmel) about some amazing new devices that can dramatically simplify the task of getting your next design into the IoT party.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

The Power of Tcl in PlanAhead

In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

latest papers and content

Cognitive Layering Technique for Low-Energy, Sensor-Rich Devices

In this week's Whiteboard Wednesdays video, Chris Rowan talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

Using the ARM AMBA Protocol

In this week's Whiteboard Wednesdays video, Avi Behar follows up on his earlier video on the ARM® AMBA® protocol family. Watch this video for a deep dive on each of the protocols in the ARM AMBA family to learn how they are commonly used.

Xylon: Face detection C-callable RTL IP with MicroZed vision kit

Xylon demonstrates face detection C-callable RTL IP with the MicroZed kit at Embedded World 2015

SDSoC Development Environment Demo

This video demonstrates how to create a simple image processing pipeline to detect motion, and to insert motion-edges into a live HD 1080p video stream running at 60 frames per second.

Massive DDR4 Memory Bandwidth with Xilinx UltraScale FPGAs

As FPGA designers, we are always looking for the maximum performance and flexibility in our designs. But, commodity DDR3 memory can be a bottleneck in many systems. In this episode of Chalk Talk, Amelia Dalton chats with Ehab Mohsen of Xilinx about the amazing performance you can get combining DDR4 with Xilinx FPGAs.

Shaving Weeks Off PCB Design Cycle Via Auto-Routing

To keep up with product refresh cycles as well as quality expectations, the Polycom hardware team decided it was time to move to auto-routing of their PCB boards, using tools including OrCAD Capture CIS for schematic design entry and synchronization/validation of parts data, Allegro PCB Designer for constraint-driven design, and Allegro PCB Router for auto-routing.

SDSoc Development Environment Backgrounder

This backgrounder describes the features and benefits of the SDSoC™ Development Environment. The SDSoC development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use an Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and 3rd party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

Introducing the SDSoC Development Environment

The SDSoC™ development environment provides a greatly simplified ASSP-like C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment.

Major Enhancements of the PCIe Gen 4 Specification

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the latest enhancements of PCI Express (PCIe) Gen 4 and how these enhancements address the goals of increased bandwidth while maintaining software compatibility and keeping power consumption and implementation costs down.

How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse

Engineering teams are under more pressure than ever before as SoCs grow more complex and design schedules become increasingly tighter. With its productivity advantages, high-level synthesis (HLS) has long been touted as part of the solution, but its sweet spot has traditionally been limited to datapath-centric blocks. Moreover, design productivity is only one part of the equation. Verification is often an even bigger hurdle. This paper discusses how HLS can be used to improve the design, verification, and reuse of intellectual property (IP). The paper also introduces a new HLS tool that provides excellent power, performance, and area (PPA) results across the digital design space.

Blu Wireless Boosts SystemC Design and Verification Productivity Using High-Level Synthesis Technology

As SoCs continue to grow in size and complexity, the SystemC design language has emerged as an effective means of design verification. High-level synthesis (HLS), in turn, is proving to be an ideal methodology to increase SystemC design and verification productivity. This paper presents a case study of how Blu Wireless Technology ramped up quickly with a working prototype of its WiGig millimeter wave baseband technology via a streamlined design and verification process based on SystemC and HLS.

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Developing Clean Efficient Power with LLC Resonant Converters with Infineon

Ready to get your black belt in DC power conversion? In this episode of Chalk Talk, Amelia Dalton chats with Sam Abdel-Rahman of Infineon about how to make a versatile, high-efficiency, LLC resonant mode power converter. So, buckle up, hit play, and get your DC on!

Compiling, Installing, and Running MIPS NDK Native Applications

Are you working on Android apps development? This app note on the MIPS NDK describes how to build Android applications in native C or C++.

Advanced Layout & Routing Techniques

Get an update from PCB Layout as this presentation walks through the latest techniques to help tackle your tough PCB design challenges. It will cover constraint management, advanced multi-signal routing, DDR implementation, automated placement & reuse, and more. View if you want learn how you can save time and reduce errors during PCB layout.

Expanding Manufacturing Verification to the Real World with LBIST

To achieve and exceed the key quality metrics for automotive devices, such as safety standards ISO 26262 and AEC-Q100, engineers are rethinking how Design for Test (DFT) methods can be re-used to test their designs throughout the chip’s lifespan. This requirement has driven resurgence in the need for logic built-in self test (LBIST), a mechanism that tests the functional logic of a chip. Cadence Encounter Test LBIST offers a unique solution in this space.

Addressing the Advantages of Embedded LTE and Advanced LTE

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of embedding a LTE and Advanced LTE analog block on the SoC to support many of the mobile applications in the market today.

Vault-Driven Electronics Design

In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how to set up a robust design-for-re-use design methodology for your team that will flow nicely with your project, won’t take much effort to set up, and will bring BIG TIME long-term benefits of design re-use, configuration management, and manufacturing handoff.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

UAV-to-Basestation Encryption

Sr. Defense Architect Jim Anderson shows how Xilinx defense-grade Virtex FPGAs enable the highest level of information assurance with Type-1 Single-chip Cryptography in a UAV application.

Power Reduction in Next-Generation UltraScale Architecture

Designed to scale from 20 nm planar technology through 16 nm FinFET and beyond, Xilinx UltraScale™ devices equip an already-successful architectural platform with numerous innovative power reduction techniques. This white paper explores the challenges of managing power efficiently, reducing device power requirements, and innovating new power solutions at the speed of Moore's law.

Solutions for Mixed-Signal SoC Verification Using Real Number Models

As old methods fall short, new techniques make advanced SoC verification possible. This paper presents mixed-signal block and IC-level verification methodologies using analog behavioral modeling and combined analog and digital solvers. It then describes analog real number modeling (RNM) and how it is used in top-level SoC verification.

Reduce Project Schedules and Increase Quality using Model Driven Development for Design, Verification, and Test

This paper shows how Model Driven Development can address common challenges in the system design, verification & testing of complex systems. Project success requires that hardware, software, and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components, which often proves to be costly in terms of time, money, and engineering resources. This paper covers such solutions that reduce project schedule while improving product release quality.

Xilinx and ARM: Zynq-7000 All Programmable SoC

Ian Ferguson, VP of Segment Marketing at ARM, introduces the Zynq®-7000 All Programmable SoC as the result of a strong partnership between ARM and Xilinx. He discusses how Zynq is opening up new markets for ARM and is alleviating the need for a multi-chip solution in many applications. Ferguson also speaks to Zynq's compatibility with leading operating systems and tools, and challenges designers to develop new and creative ways to design with a Zynq-7000 SoC.

ASIC Prototyping Simplified

To use current solutions for application-specific integrated circuit (ASIC) prototyping using field-programmable gate arrays (FPGAs), you either have to create custom boards or buy off-the-shelf FPGA boards. Off-the-shelf boards don’t satisfy the requirements for complex systems on chips (SOCs), and they’re expensive and lack scalability. Cadence Allegro FPGA System Planner fills the gap, offering a simplified approach to ASIC prototyping.

Next-Generation Packaging for CRM Applications

With smaller electronics, more options can be fit into the package, allowing for features such as RF transceivers for wireless communication, advanced sensors to optimally time pacing and defibrillation shocks and backup systems in case the main system fails. While integrated circuits (ICs) have taken advantage of advances in dense packaging, such as die stacking, in most cases the discrete components remain unchanged. Market pressures are now forcing improvements in the current discrete packaging.

3D Design and Viewing = STEP Support

With the PCB Editor’s 3D Viewer, the user can see a true 3D graphical view of the PCB. The capability of including enclosures associated with the board is also provided for positioning and collision detection. See how OrCAD PCB Editor makes that possible and allows you to bridge the gap between ECAD and MCAD with STEP model support.

Lattice Saves Millions, Avoids Respins and Product Delays with Sigrity Tools

Lattice is a global leader in delivering ultra-low power FPGAs for manufacturers of smartphones, small cell networking equipment, and industrial applications. For its customer base, fast time to market, low power, and low cost are important considerations. In this video, Maryam Shahbazi of Lattice's Systems Development Group talks about how the company relies on Cadence® Sigrity™ tools to model its power delivery network, solve power integrity issues, and improve voltage margins.

Verification Methodologies (Made Easy)

Most FPGA designers don’t know much about formal methodologies for verification. It’s too bad, because today’s complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.

Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.


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