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Routing Interfaces Quickly & Efficiently on PCBs

In today's PCB designs, interfaces such as DDR pose major challenges for layout. Issues like timing and signal integrity can be tricky for even the most experienced designer. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about routing those tricky bits using a combination of automatic and manual routing techniques.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Intelligently Expanding Microprocessor Connectivity Using Low-cost FPGAs

Whether they be CPUs, microprocessors or microcontrollers, microprocessors are an indispensable component in modern electronic system design. However, as systems become more complex and host a wider array of features and user interfaces, system architects using mid-range microprocessors in particular typically face three key challenges connecting the microprocessor, or microprocessors, they are using to the rest of their system: implementing more than 150 general purpose I/Os (GPIO), finding cost effective solutions in the 100 to 150 GPIO range, and matching available I/O peripherals with system needs.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

It really isn't important to simulate your PCB design - as long as you don't care about re-spins, signal integrity, cost... OK, actually, there are many good reasons to simulate your board. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about simulating your board design using PADS. It may make you re-think your board design strategy.

Protium Rapid Prototyping Platform

Building a robust prototype involves a lot more than just throwing a bunch of big FPGAs on a board or in a box. In fact, success of a prototype is a lot more about the system surrounding the boards - the tools, design flow, and IP that make the whole thing come up easily and work smoothly. In this episode of Chalk Talk, Amelia Dalton talks to Juergen Jaeger of Cadence about the new Protium Rapid Prototyping Platform from Cadence, and how it can simplify your prototyping process.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Lowering the Total Cost of Ownership in Industrial Applications

This white paper uses a design example to demonstrate that FPGAs are not only a more flexible option than discrete MCU, DSP and ASSP products, but also provide a lower total cost of ownership (TCO) as measured by development, enhancement, replacement, and maintenance costs over the lifetime of a system.

Multiplying the Value of 20nm with UltraScale Devices: Doing More for Less

Xilinx is multiplying the value of 20nm with the UltraScale™ architecture and associated family of FPGAs and 3D ICs. Whether viewed from almost every attribute at the chip level or viewed when integrating multiple chips into one or fewer chips at the system level, you will find compelling value metrics as you migrate to an UltraScale solution. UltraScale architecture and Vivado® Design Suite are co-optimized to enable a device utilization target of 90%, which can result in up to a 30% effective cost advantage for the next generation of smarter, high performance systems in: Packet processing: Multi-hundred gigabit throughput Waveform processing: Multi-teraMAC throughput Image and video processing: 8K4K image and video processing and transport High performance computing: Multi-teraflop throughput Learn More about potential chip and system level value multipliers.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

OpenCL on FPGAs for GPU Programmers

In this white paper, Acceleware introduces parallel programming targeting Altera® FPGAs using the OpenCL™ framework to graphics processing unit (GPU) programmers. This white paper provides a brief overview of OpenCL, discusses the Altera FPGA architecture and its benefits, and explains how OpenCL kernels are executed and optimized on FPGAs versus GPUs.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

Troy Scott, Product Marketing Manager, and Peter Zhang, R&D Engineer, explain RTL debug features available in ProtoCompiler.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

chalk talks

Design @ MachXO2 Speed

Just about every design needs one - that magic, do-anything part that can connect nearly any two things together and can aggregate all those messy, left-over functions on our board. Today's low density PLDs have remarkable capabilities at a tiny cost and power budget. In this episode of Chalk Talk HD Amelia Dalton chats with Steve Hossner (Lattice Semiconductor) about the amazing capabilities of Lattice’s latest low density PLD line, the MachXO2.

It's 2022: Do You Know What Your FPGA Is?

Does the definition of "FPGA" seem like a moving target? Over the past few years, there has been phenomenal progress in FPGA technology - going from simple glue logic to impressive programmable systems-on-chip. Today's FPGAs are some of the most powerful and flexible devices ever built. But, what will your FPGA look like ten years from now? In this episode of Chalk TalkHD Amelia Dalton chats with Umar Mughal of Altera about the past, present, and future of this exciting technology.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality

In this episode of Chalk TalkHD Amelia chats with Bob Potock (Kozio) about how you can save yourself a bunch of headaches at prototype time and how Kozio’s VTOS (Verification and Test Operating System) can solve all of your embedded design prototyping problems.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

How to Design a Sigma Delta Mixer Circuit

In parts 1 & 2 of this 3-part Chalk Talk series, we talked about how Triad Semiconductor can save you 75%, or even as much as 99% in your next mixed-signal ASIC design. But, what good is savings if you don't know what you can design with it? In this third episode of our 3-part Chalk Talk series, Amelia and Reid Wender of Triad Semiconductor have fun taking ViaDesigner out for a spin - designing a sigma delta mixer.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Overcome the Challenges of Highly Constrained Designs

Many of today's high-performance board designs have complex timing constraints, and meeting all those constraints can be a significant design challenge. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about advanced design techniques with PADS that will help get you to design closure faster and with fewer headaches on complex, highly-constrained boards.

latest papers and content

Flexible Design Reuse and Replication for PCB Editor

As PCB Designs become more complex and project timelines more compressed, it is important to identify opportunities to enhance design processes. See a quick introduction to CircuitSpace and learn how this productivity tool can help you reduces PCB layout time by up to 50%.

Automated Impedance and Coupling Checks

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance so you can sign off in confidence. In this video you will learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. In this example OrCAD PCB Editor was used as his tool of choice but the options are not limited to that. No models needed!

How to automatically replace LEF abstracts with GDS IP

Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification. This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

How to waive DRC results using Calibre RVE

This video will show you how to waive some violations using Calibre RVE and re-use the waivers' information in the new set of results.

DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

Multi-Board Electrical and Thermal Co-Simulation Using PowerDC

Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.

TimingDesigner: Complex Diagrams

This video showcases TimingDesigner capabilities, especially for building complex diagrams. It will cover derived clocks, derived signals, and differentially ended signals which will include state decodes, measure events, guarantees and skews. Lastly it will cover complex diagram capabilities in the parameter spreadsheet.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

How to easily setup Calibre in Virtuoso for multiple cell windows

This video shows how to setup Calibre Interactive to quickly select from multiple cells open in Virtuoso. Previously there was not a convenient way to setup Calibre Interactive when you wanted to run Calibre in different cells that are simultaneously open in the same Cadence session but now the Layout Cell Browser capability in Calibre Interactive provides an easy and convenient way to select from multiple cells open in Virtuoso.

How to Debug Double Patterning results using Calibre RealTime

This video shows how to easily debug Double Patterning results in Calibre RealTime by using the CTO file to assign different highlight colors to the warning and conflict ring results and to the mask1 and mask2 output layers.

Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

TimingDesigner Simple Diagrams

This video focuses on drawing simple diagrams in the TimingDesigner program. The presentation covers drawing clocks, signals and buses. It then moves on to edge events, which include delays and constraints. Lastly it covers edge events and the Parameter spreadsheet where it looks at variables, functions, and shows an example of a diagram of a Sharc DSP processor.

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Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs

Since their introduction in the mid-1980s and across all end markets, CPLDs have been design engineers’ favorite choice for control path applications. Taking into account today’s severe pressure to lower costs and power consumption, this white paper examines how Altera® MAX® V CPLDs provide solutions for the top five control-path applications.

Implementation of 9x9 Multiplications, Wide-Multiplier, and Extended Addition Using IGLOO2/SmartFustion2 Mathblock App Note

This application note highlights design guidelines and different implementation methods to achieve better performance results while implementing wide-multipliers, 9-bit×9-bit multiplications, and extended addition with the IGLOO2/SmartFusion2 mathblock (MACC). The 9-bit×9-bit multiplications, wide-multiplier, and extended addition are ideal for applications with high-performance and computationally intensive signal processing operations. Some of them are finite impulse response (FIR) filtering, fast fourier transforms (FFTs), and digital up/down conversion.

High-Definition Video Reference Design Application Note

Learn about using the Altera® high-definition video reference designs to deliver high-quality up, down, and cross conversion (UDX) designs for standard-definition (SD), high-definition (HD), and 3 gigabits per second (Gbps) video streams in interlaced or progressive format. These reference designs are highly software and hardware configurable, enabling rapid system configuration and design. The designs target typical broadcast applications such as switcher, multiviewer, converter, and video conferencing products.

SDNet Backgrounder

Read this document if you wish to understand the broad capabilities of Software Defined Specification Environment for Networking (SDNet) and the need for ‘Softly’ Defined Networks.

Xilinx Agile Mixed Signal

In this episode of Chalk TalkHD Amelia chats with Steve Logan (Xilinx ) and they're going to tell you all about Agile Mixed Signal, and how it can dramatically improve the capabilities of your next FPGA design.

Expect a Breakthrough Advantage in Next-Generation FPGAs

A product strategy that uses a tailored approach drawing upon using different process technologies, architectures, and integration options targeted to different applications will give hardware architects the best possible choices and solutions. This white paper covers examples of why telecommunication bandwidth and the infrastructure behind it is driving FPGA capabilities, business challenges of ASICs and ASSPs, and how a tailored approach for programmable logic devices (PLDs) provide a leap in FPGA capabilities. This paper also outlines Altera’s generation 10 portfolio of next-generation FPGAs and SoCs that seeks to provide a breakthrough in capabilities and advantages across a variety of different applications.

FPGA Plug-and-Play Design with the AXI-4 Common Interconnect

This video offers details of Xilinx support for the AXI-4 Common Interconnect and highlights the benefits of increased designer productivity, greater IP availability, and extended flexibility to achieve performance and system goals. Using the Xilinx Targeted Design Platforms to illustrate these benefits, Xilinx technical experts describe how support for the AXI-4 Common Interconnect is the cornerstone for the move to FPGA Plug-and-Play design.

Designing with SmartFusion Intelligent Mixed Signal FPGAs

Watch this short video introducing the software tools and design flows for implementing SmartFusion™ intelligent mixed signal flash FPGA designs, including devices, hardware kits and ecosystem to get you started.

Injecting Automation into Verification - Assertions

What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

Supporting Digital Television Trends with Next-Generation FPGAs

What do the following items have in common: iPhones, Avatar 3D, digital SLR cameras, and LCD digital televisions? They are all evidence that consumers strongly prefer products with “stunning” visuals. This white paper shows how these trends towards new features and faster introduction rates of new models are fueling increased FPGA use within high-definition television electronics. The digital television market is growing, with the number of LCD-based digital televisions growing at 22% CAGR.

Industry's First DDR4 Controller and Interface Running at 2400 Mb/s

This demonstration showcases a DDR4 memory interface running at and above 2400 Mb/s with the Kintex® UltraScale™ FPGA. The memory interface will demonstrate adequate operating margin while running under stressful conditions, ensuring robust operation in the presence of voltage, process or temperature variation.

Easily Support WDR CMOS Image Sensor Processing with Low-Cost FPGAs

High-definition (HD) wide dynamic range (WDR) CMOS image sensors are ideal for applications like video surveillance cameras. And for the underlying technology, FPGAs are optimal because they deliver the high bandwidth these sensors demand. In this 7-minute video, you'll see how an FPGA-based platform easily performs complex image processing to support WDR CMOS image sensors.

OpenCL on FPGAs for GPU Programmers

In this white paper, Acceleware introduces parallel programming targeting Altera® FPGAs using the OpenCL™ framework to graphics processing unit (GPU) programmers. This white paper provides a brief overview of OpenCL, discusses the Altera FPGA architecture and its benefits, and explains how OpenCL kernels are executed and optimized on FPGAs versus GPUs.

SystemVision® Multi-discipline System Verification Datasheet

The SystemVision multi-discipline collaboration environment lets you explore concepts, validate performance specifications, investigate architectural partitions, and integrate implementation-level details, all in an easy-to-use virtual prototyping environment. Focus on a single design domain, or combine multiple domains, for full-system verification.

Implementing PCI Express Bridging Solutions in an FPGA

As system bandwidths increase, more applications are moving to SERDES-based interfaces like PCI Express. Newer generation FPGAs with embedded SERDES, like the LatticeECP3 devices, can be used to support a variety of serial protocols like PCI Express, providing a single FPGA platform for multiple designs.

A Call to Action: How 20nm Will Change IC Design

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a “prevent, analyze, and optimize” methodology.

Using FPGAs to Render Graphics and Drive LCD Interfaces

This paper describes the use of FPGAs to add a LCD and GUI display to any embedded system. Unlike fixed processor device implementations, this approach is scalable and supports any display interface. Graphics can be generated by any external processor, embedded processor, or hardware graphics acceleration engine integrated into the same FPGA design. The benefits of FPGA implementation and available tools and IP are described, and links to reference designs and solution providers are given.

Accelerated Design Productivity with the Kintex-7 FPGA Display Kit

In this episode of Chalk TalkHD Amelia gets into the guts of display technology with Aaron Behman of Xilinx. From the newest standards to the details of 4K2K, we will tell you how FPGAs are uniquely capable of meeting the extreme performance and power challenges posed by current and emerging video standards.


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