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i.MX 6SoloX – Freescale’s New Heterogeneous Multicore Applications Processor

Many applications today need both an applications processor AND a real-time MCU. But, most solutions don't offer both on the same chip. In this episode of Chalk Talk, Amelia Dalton chats with Amanda McGregor of Freescale about a new application processor that combines an ARM Cortex-A9 core with the efficiency and real-time capability of the Cortex-M4.

Efficient Product Creation with Allegro and Sigrity Solutions

Being a PCB Expert isn't enough anymore. With today's interconnected systems, you need to design at the product level to be competitive. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence Design Systems about product design with Cadence's Allegro and Sigrity tools.

Accelerating Your Analog Output Design

Eventually, most of our designs need to control something in the real world. That means we have to bust out of our safe little digital realm, and drive some analog actuators or something similar. But, building that analog output section from scratch can be a real challenge. In this episode of Chalk Talk, Amelia Dalton talks to Bill Laumeister of Maxim Integrated about the Analog Output Design Accelerator Kit (MAXREFDES24EVSYS), a complete platform for easy evaluation that requires no lab equipment.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Design Control, Data & Comparison with PADS Design Archive

A solid design data archive and management system can make a world of difference in your PCB design productivity. A good strategy enables re-use, eliminates costly errors, and allows you to get the most from your team's engineering efforts. In this episode of Chalk Talk, Amelia Dalton chats with Jim Martens of Mentor Graphics about design data management in Mentor's popular PADS system.

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Sigrity PowerSI Tackles SSO Noise: Customer Success Story

AEI Systems needed to perform a worst case SSO analysis to screen their design and verify that defects and deficiencies would be eliminated prior to test, production and delivery. In doing so, they found that Cadence Sigrity PowerSI was the only tool tested that was able to provide the close correlation to the actual measurement needed to validate the RTAX board example. Click to see the process and results AEI Systems saw using Sigrity PowerSI to successfully evaluate worst case SSO noise.

Kintex UltraScale DSP Kit with 8 Lane JESD204B interface

The video highlights the Xilinx® Kintex® UltraScale™ FPGA Analog Devices JESD204B DSP Kit featuring the Xilinx Kintex UltraScale KCU105 development board with the KU40 device paired up with the Analog Devices AD-FMCDAQ2-EBZ high-speed analog FMC module. An 8 lane JESD204B interface is used to interface the data converters to the FPGA using GTX serial transceivers at the full 12.5 GSPS line rate. Xilinx devices are the world’s first to support the full JESD204B line rate across all device speed grades for mid-range JESD204B solutions, and the only all programmable solution available today at 20nm.

Connecting ZYNQ-7000 All Programmable SoCs with TE Connectivity Interconnect Products

New SoCs like the Xilinx Zynq are changing the industry - with new levels of functionality, flexibility, performance, and power efficiency. But, to take advantage of this new technology you'll need connectivity solutions that are up to the task. In this episode of Chalk Talk, Amelia Dalton chats with Mark Bell from TE Connectivity about plugs, connectors, antennas, and other connectivity solutions for today's most demanding designs.

What’s New in PSpice 16.6

In this webcast Matthew Harms demonstrates the new features in version 16.6 of Cadence PSpice. Matthew covers three major areas: productivity enhancements, core enhancements, and TCL Integration. This webcast covers most of these features with an explanation and a short demonstration.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

PCB Design demands a great deal more care these days. Signal and power integrity are just some of the realities that board designers must contend with these days. In this episode of Chalk Talk, Amelia Dalton talks with Brad Griffin of Cadence Design Systems about the integration of these important analysis capabilities into the PCB design process.

Product-Centric Design with Virtual Prototyping

As engineers, it's easy to get the feeling that your PCB is the center of the design universe. But, it's important to remember that we are designing products, not just boards, and a product-centric design methodology is essential to creating the competitive products that customers demand. Product level virtual prototyping validates that your detailed design approach can support the product requirements. In this episode of Chalk Talk, Amelia Dalton and Bob Potock explore the concept of product-centric design with virtual prototyping and highlight how it differs from traditional, PCB-centric design.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

chalk talks

It's 2022: Do You Know What Your FPGA Is?

Does the definition of "FPGA" seem like a moving target? Over the past few years, there has been phenomenal progress in FPGA technology - going from simple glue logic to impressive programmable systems-on-chip. Today's FPGAs are some of the most powerful and flexible devices ever built. But, what will your FPGA look like ten years from now? In this episode of Chalk TalkHD Amelia Dalton chats with Umar Mughal of Altera about the past, present, and future of this exciting technology.

Low-Power Estimation & Verification With ZeBu

Power consumption is one of the key drivers in system design today, and it’s about time we had a way to estimate and verify the power used by our design. In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti (Synopsys) about how to verify and estimate power consumption with the ZeBu emulator.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

Adding Wi-Fi to Your FPGA Design - Building a Connected Device

In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.

Vivado Design Suite: Integrated Design Environment

Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado Design Suite with Brian Lay of Xilinx.

Effective Version Control for Electronic Design

When it comes to our hardware engineering projects, we need to keep our design data well organized. In the software world, this is accomplished with the help of version control systems. Unfortunately, most of us don’t learn version control for hardware design. In this episode of Chalk TalkHD Amelia chats with Ben Jordan of Altium about how effective version control can help every step of the design process, enable team design, manage versions and configurations, and keep our project from spiraling out of control.

latest papers and content

Meet PPA and Turnaround Time Requirements at Advanced Nodes with Innovus Implementation System

Today's complex IC designs demand a new generation of high-capacity, high-performance implementation tools. In this episode of Chalk Talk, Amelia Dalton chats Yufeng Luo of Cadence Design Systems about the incredible innovations in Cadence's new Innovus implementation suite.

Inductance-to-Digital Converters Revolutionize Position & Rotation Sensing

Inductive sensing is a reliable, accurate, and robust technology for a wide variety of position, rotation, metal detection and spring compression measurement applications. In this episode of Chalk Talk, Amelia Dalton chats with Anjana Govil of Texas Instruments about how you can use inductance-to-digital converters to take advantage for inductive sensing in your next design.

Connecting ZYNQ-7000 All Programmable SoCs with TE Connectivity Interconnect Products

New SoCs like the Xilinx Zynq are changing the industry - with new levels of functionality, flexibility, performance, and power efficiency. But, to take advantage of this new technology you'll need connectivity solutions that are up to the task. In this episode of Chalk Talk, Amelia Dalton chats with Mark Bell from TE Connectivity about plugs, connectors, antennas, and other connectivity solutions for today's most demanding designs.

Zynq-7000 All Programmable SoC: Embedded Design Tutorial

To help accelerate your Zynq®-7000 All Programmable SoC embedded development, Xilinx has introduced a new Embedded Design Tutorial, a hands-on guide designed to help walk you through embedded system design. The guide provides opportunities to work with tools under discussion, examples and an explanation of what is happening behind the scenes.

UltraFast Embedded Design Methodology Guide (REVISED)

Xilinx is building on the success of its UltraFast™ Design Methodology with the new UltraFast Embedded Design Methodology Guide. The new Guide enables embedded design teams to improve productivity with a documented methodology for the creation of smarter systems leveraging Zynq®-7000 All Programmable SoCs.

Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs

Xilinx discusses how programmable logic provides the partial reconfiguration capabilities, large number of high speed analog IOs and mix signal capabilities to build high density, scalable and flexible 500G/1T line cards today.

Xilinx and Ixia present 400GE and 25GE testing solutions at OFC 2015

In this live presentation from OFC 2015, Xilinx talks with Ixia about how they surmounted the many obstacles to efficient 400GE and 25GE testing by leveraging Xilinx’s All Programmable devices to get the Ixia 400GE and 25GE tester families to market quickly. Presented by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.

i.MX 6SoloX – Freescale’s New Heterogeneous Multicore Applications Processor

Many applications today need both an applications processor AND a real-time MCU. But, most solutions don't offer both on the same chip. In this episode of Chalk Talk, Amelia Dalton chats with Amanda McGregor of Freescale about a new application processor that combines an ARM Cortex-A9 core with the efficiency and real-time capability of the Cortex-M4.

UltraScale Integrated 100G Ethernet IP for 10x10G and 4x25G

This video demonstrates how using an integrated Ethernet MAC can save power, integration time and logic utilization while delivering the highest possible flexibility. The UltraScale™ Integrated 100G Ethernet IP supports both CAUI-4 and CAUI-10 interfaces to CFP, CFP2, CFP4 and other pluggable optics. As shown in this video, the IP can easily and dynamically swap between interfaces.

Kintex UltraScale DSP Kit with 8 Lane JESD204B interface

The video highlights the Xilinx® Kintex® UltraScale™ FPGA Analog Devices JESD204B DSP Kit featuring the Xilinx Kintex UltraScale KCU105 development board with the KU40 device paired up with the Analog Devices AD-FMCDAQ2-EBZ high-speed analog FMC module. An 8 lane JESD204B interface is used to interface the data converters to the FPGA using GTX serial transceivers at the full 12.5 GSPS line rate. Xilinx devices are the world’s first to support the full JESD204B line rate across all device speed grades for mid-range JESD204B solutions, and the only all programmable solution available today at 20nm.

Reducing System BOM Cost with Xilinx's Low-End Portfolio

A system’s bill of materials is made up of interdependent component costs, meaning a holistic approach is required to ensure lowest overall BOM cost. With a balance of the right features and capabilities, Xilinx’s Low-End All Programmable Portfolio offers system designers numerous cost-reduction strategies for high volume applications in the industrial, medical, automotive, consumer, and communications markets, among others. This white paper discusses these strategies with a variety of application examples.

SDSoC Development Environment: Optimization & Debug

Part 2 of 2 of an introduction to the SDSoC™ Development Environment: This video reviews implementation challenges and how SDSoC helps solve those challenges, take a fully implemented design and modifying it to further optimize the accelerated functions. Then reviews how SDSoC enables interactive debug on an implemented design running on an evaluation board.

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OrCAD Now! Signal Integrity Presentation

Learn about the unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. This will also show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations.

Integrated Interlaken operating at 150 Gb/s in UltraScale FPGAs

This Virtex® UltraScale™ FPGA demonstration shows the newly integrated Interlaken IP core running at 150Gb/s over 12 lanes. By integrating Interlaken, Xilinx is able to reduce power consumption, logic utilization, and design complexity for one of the most popular protocols in networking today.

Allegro 16.5 Powers up Allegro PCB PDN Analysis

This is a Cadence blog post about the launch of the Allegro PDN Analysis and what it will mean for PCB designers.

Automotive Top Ten - Ten Points to Consider When Using Logic in Your Next Automotive Design

Automotive electronics designers have been turning more frequently to programmable logic solutions to meet the needs of their next generation designs. FPGAs offer time-to-market benefits along with simplified qualification and greater flexibility in comparison to historic ASIC-based solutions. Actel is a leading supplier of FPGAs to the automotive industry. Actel parts are being used in the most demanding mission-critical systems, such as powertrain and safety subsystems, in addition to infotainment and body electronics designs.

A Platform for Reducing Verification Time and Improving Reliability of Embedded System Hardware

In this whitepaper the author reviews how leveraging VTOS during the prototype phase can assist engineers in overcoming the challenges design complexity exerts on product development, manufacturing, and overall time-to-market. Readers will gain insight into how they can replace today’s ad-hoc board level verification approaches with an ordered methodology that enables designers to automatically validate their own hardware designs, optimize system performance, and simplify the process of integrating new hardware with new software.

Graphics Rendering and Video Processing with Altera SoC and Helio View Dev Kit

For performance-critical applications like graphics and video rendering, the partitioning between software and hardware can be a pivotal decision. Today, exciting new devices allow us to make and evaluate those tradeoffs more easily than ever. In this episode of Chalk Talk, Amelia Dalton talks to Troy Jones (Macnica Americas) and Todd Koelling (Altera) about creating video and graphics applications using the Helio View development board with Altera SoC FPGAs.

100G Ethernet Packet Parsing with Spacetime

Designing 100G Ethernet is a daunting challenge. Timing, power, latency, and throughput all fight with each other, and it's easy to fall into a design trap with a solution that doesn't offer a good compromise. In this episode of Chalk Talk, Amelia Dalton chats with Parsun Raha about the challenges of 100G (and beyond), and how those conflicting design goals can be met by Tabula's innovative Spacetime architecture.

The Industry's First 20nm and UltraScale FPGAs and 3D ICs

The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system level performance for the most demanding applications.

UltraFast Embedded Design Methodology Guide (REVISED)

Xilinx is building on the success of its UltraFast™ Design Methodology with the new UltraFast Embedded Design Methodology Guide. The new Guide enables embedded design teams to improve productivity with a documented methodology for the creation of smarter systems leveraging Zynq®-7000 All Programmable SoCs.

World's First 28nm FPGA from Xilinx Shows Key 10Gbps SERDES Functionality

The first-ever 28nm FPGA demonstrates major design functionality within the first 48 hours, including 10Gbps eye quality.

Getting Started Using Kintex-7 FPGAs for DSP

In this episode of Chalk TalkHD Amelia chats with Tom Hill of Xilinx about their new Kintex-7 DSP development kits that will finally get you onto the rocket-coaster of FPGA-powered DSP.

Xilinx 7 series FPGAs

Xilinx 7 series FPGAs offer breakthrough power, performance, & dramatically reduced development time.

Zynq-7000 All Programmable SoCs Deliver Unmatched Performance and Power

Xilinx Zynq®-7000 All Programmable SoC devices fuse a fast processor system (PS) based on two 1GHz ARM Cortex™-A9 MPCore processors with the industry’s fastest and most advanced 28nm programmable logic (PL) fabric, a large on-chip memory, multiple high-speed serial transceivers, numerous hardened peripheral IP cores including DDR and Flash memory controllers, and an on-chip analog-processing block that incorporates two 1Msamples/sec A/D converters. Zynq-7000 devices offer unmatched performance with low operating power.

What’s New in Capture 16.6

OrCAD 16.6 is here. Watch this free webcast to learn what's new in the latest release of OrCAD Capture, including enhancements in productivity, usability, and features. Highlights: • Database Enhancements • CIS Explorer Improvements & Customization • Tcl Expansion • SI Integration • Improved Symbol Creation

4 Steps to Bring Up a CFP2 Optical Module with a Virtex-7 HT FPGA

This video demonstrates the world's first all programmable heterogeneous FPGA interfacing to a CFP2 Optical Module. The demo walks through 4 steps required to bring up the system and then shows how Xilinx simplifies the integration process.

Pattern Matching:  Blueprints for Further Success

Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process.

Creating IP Subsystems with Vivado IP Integrator

Learn how Vivado IP Integrator can be used to rapidly build a video sensor processing pipeline design using AXI4, a MicroBlaze processor and an external DDR3 memory interface. Vivado IP Integrator can be used to quickly build and reuse IP and IP subsystems. Watch the video now to learn more!

Is Your Memory Design Correct and Reliable?

Learn how quickly and easily you can run a comprehensive memory test and uncover design and reliability issues. In this video, a memory failure is detected only in "burst" mode, while passing all other tests. A second development board passes all the tests.


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