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Designing for Low Power

Power consumption is becoming an increasingly important variable when it comes to calculating OPEX and carbon footprint for telecom infrastructure projects. For example, on average, each fully loaded 3G cell site costs approximately $1600/yr US or $3200/yr in Europe. This suggests a typical European operator running 20000 cell sites would consume 58MW, which translates to about $62M USD per year. In addition to these costs, the level of consumption per cell site leads to an estimated 11 tons of carbon dioxide emissions per cell site per year. For these operators, power equals cost. FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. 

For example, to minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3’s static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. 

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