Efficiently supporting ever-increasing system bandwidth needs by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This paper is an architectural exploration of SERDES challenges and solutions for 12.5-Gbps backplanes and next-generation optical modules at 28 Gbps. It describes the direction of the 10- to 28-Gbps transceiver industry, highlights challenges, and introduces 28-nm silicon and productivity solutions that address these challenges.
Author: Salman Jiva, Product Marketing Manager, Altera Corporation
As Product Marketing Manager for Altera’s high-end FPGA product lines, Salman Jiva is responsible for the technical marketing, positioning and management of high-speed SERDES and signal integrity for Altera FPGAs. Prior to joining Altera, he spent six years at Cisco Systems as an ASIC signal-integrity engineer for their enterprise line of switches. Mr. Jiva holds an MS in Electrical Engineering from Santa Clara University with a concentration in communication systems.
