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Designing a Power Distribution Network for High-End FPGAs

Progress to smaller FPGA process geometries has led to shrinking noise margins and lower voltages. These changes mandate higher currents, tighter voltage tolerances, and management of multiple power rails. Every board designer has to learn how to deliver clean power to the FPGA, as making the wrong choice can severely reduce functionality and performance.

This webcast shows a scientific way to design an effective power distribution network (PDN) on high-end FPGAs while minimizing board complexity, decoupling requirements, and system costs.

View this webcast to learn:

  • Decoupling schemes for an effective PDN design
  • Factors affecting PDN design
  • Altera’s PDN tool and design flow, including a design example based on the Stratix® IV FPGA Development Kit
  • Competitive comparison on bypassing requirements

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Today we embark on an exciting journey as we transition to Altera, an Intel Company. In a world of endless opportunities and challenges, we are here to provide the flexibility needed by our ecosystem of customers and partners to pioneer and accelerate innovation. As we leap into the future, we are committed to providing easy-to-design and deploy leadership programmable solutions to innovators to unlock extraordinary possibilities for everyone on the planet.

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