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GEN2 Serial RapidIO and Low Cost, Low Power FPGAs
System designers will continue to be under pressure to produce higher performance systems yet maintain lower build and operational costs. DSP and Network Processing Unit (NPU) devices, coupled with low cost, low power FPGAs like the Lattice ECP3 that support Gen2 Serial RapidIO (SRIO), can provide an ideal platform for meeting these challenges.
White Paper sponsored by Lattice
Achieving Lowest System Cost with Midrange 28 nm FPGAs
Increased capability does not have to increase your cost. Arria V FPGAs provide the highest bandwidth and the most hard IP at the lowest price. In addition, by designing with Arria V FPGAs, you can save system costs, operating costs, and manufacturing costs.
White Paper sponsored by Altera
Embedded Design Verification Best Practices Short Video
Watch this short video on Embedded Design Verification Best Practices and learn how to verify embedded designs for correctness and reliability utilizing a NEW approach employing a Verification and Test OS (VTOS™).
Customer Private Label Program
Customers have prototyped their products utilizing Microsemi FPGA & cSoCs and then quickly went to production on the same platform. This ensures design consistency and gets product to their customers on time as scheduled. Microsemi’s private label program goes a step further and provides the ability to custom mark devices with company logo’s and part numbers. Furthermore, our devices do not require an external EEPROM for boot-up configuration, thus the end product can be sold as single IC solution. This approach provides numerous levels of security including prevention of reverse engineering coupled with 128-bit encryption keys to unlock and reprogram your device for field upgradability when the need arises.
IP and Process Solutions for Energy-efficient PMICs
In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.
Chalk Talk sponsored by ARM
Is Your Memory Design Correct and Reliable?
Learn how quickly and easily you can run a comprehensive memory test and uncover design and reliability issues. In this video, a memory failure is detected only in "burst" mode, while passing all other tests. A second development board passes all the tests.
FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit
In this episode of Chalk Talk HD, Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.
Chalk Talk sponsored by Xilinx
Maximize Design Productivity With PCIe/104 FPGA/Processor
In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.
Chalk Talk sponsored by Kontron
Teradici Success Story
Synopsys and Teradici: ASIC Prototyping Made Fast and Efficient with Synplify Premier
White Paper sponsored by Synopsys
It's 2022: Do You Know What Your FPGA Is?
Does the definition of "FPGA" seem like a moving target? Over the past few years, there has been phenomenal progress in FPGA technology - going from simple glue logic to impressive programmable systems-on-chip. Today's FPGAs are some of the most powerful and flexible devices ever built. But, what will your FPGA look like ten years from now? In this episode of Chalk TalkHD, Amelia Dalton chats with Umar Mughal of Altera about the past, present, and future of this exciting technology.
Chalk Talk sponsored by Altera
chalk talks
Spartan-6 FPGAs in Video Designs
In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.
Chalk Talk sponsored by Xilinx
Scalable Smart Debugging With ZeBu-Server
In this episode of Chalk TalkHD, Amelia chats with Lauro Rizzatti of EVE about how EVE's ZeBu emulation technology can help you find that one last bug in even the biggest of designs.
Chalk Talk sponsored by EvE
Hierarchical Design Flows: Design Preservation & Team Design
In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.
Chalk Talk sponsored by Xilinx
Adding Wi-Fi to Your FPGA Design
In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.
Chalk Talk sponsored by Altium
Intel Atom™ Processor with built-in Altera Arria® FPGA
In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.
Chalk Talk sponsored by Arrow
IP and Process Solutions for Energy-efficient PMICs
In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.
Chalk Talk sponsored by ARM
latest papers and content
FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit
In this episode of Chalk Talk HD, Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.
Chalk Talk sponsored by Xilinx
It's 2022: Do You Know What Your FPGA Is?
Does the definition of "FPGA" seem like a moving target? Over the past few years, there has been phenomenal progress in FPGA technology - going from simple glue logic to impressive programmable systems-on-chip. Today's FPGAs are some of the most powerful and flexible devices ever built. But, what will your FPGA look like ten years from now? In this episode of Chalk TalkHD, Amelia Dalton chats with Umar Mughal of Altera about the past, present, and future of this exciting technology.
Chalk Talk sponsored by Altera
Is Your Memory Design Correct and Reliable?
Learn how quickly and easily you can run a comprehensive memory test and uncover design and reliability issues. In this video, a memory failure is detected only in "burst" mode, while passing all other tests. A second development board passes all the tests.
Embedded Design Verification Best Practices Short Video
Watch this short video on Embedded Design Verification Best Practices and learn how to verify embedded designs for correctness and reliability utilizing a NEW approach employing a Verification and Test OS (VTOS™).
Troubleshooting and Fast Fault Isolation with VTOS
Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.
Sponsored by: Kozio
A Platform for Reducing Verification Time and Improving Reliability of Embedded System Hardware
In this whitepaper the author reviews how leveraging VTOS during the prototype phase can assist engineers in overcoming the challenges design complexity exerts on product development, manufacturing, and overall time-to-market. Readers will gain insight into how they can replace today’s ad-hoc board level verification approaches with an ordered methodology that enables designers to automatically validate their own hardware designs, optimize system performance, and simplify the process of integrating new hardware with new software.
White Paper sponsored by Kozio
Memory Testing 101 – Avoid the Train Wreck
Memory is fundamental to the “sanity” of an embedded system. Inadequate memory testing is posing critical challenges to designers and indirectly manifesting considerable consequences at some of the biggest names in the electronics business. Today’s embedded systems consist of multiple memory types including SDRAM, LPDDR2, DDR3, FLASH, EEPROM and more, along with multiple protocols including GPIO, PCI, SPI and I2C. This paper will review a comprehensive and flexible Verification and Test Operating System (VTOS™) solution that includes a suite of memory tests that verifies the design for correctness and production readiness.
White Paper sponsored by Kozio
Customer Private Label Program
Customers have prototyped their products utilizing Microsemi FPGA & cSoCs and then quickly went to production on the same platform. This ensures design consistency and gets product to their customers on time as scheduled. Microsemi’s private label program goes a step further and provides the ability to custom mark devices with company logo’s and part numbers. Furthermore, our devices do not require an external EEPROM for boot-up configuration, thus the end product can be sold as single IC solution. This approach provides numerous levels of security including prevention of reverse engineering coupled with 128-bit encryption keys to unlock and reprogram your device for field upgradability when the need arises.
System Management
Semiconductor devices are prone to failure even after they have been tested, packaged and shipped by the semiconductor vendor. The main factors that contribute to device failure in a system are electrically, environmentally and mechanically induced failures. Because mechanical failures are almost impossible to mitigate at the electrical or electronic design stage the following discussion focuses on electrical and environmental stresses.
Sponsored by: Microsemi
Power Supply Management in High-Availability Systems
One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD, Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.
Chalk Talk sponsored by Microsemi
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Reliable Reset Generation for TI DSP Processors
Every requires a reset generator circuit or IC to start up from a fixed condition after the supplies are turned on, and prevent the processor from executing instructions incorrectly and causing flash memory corruption. Traditional, simple, single-supply reset generators were adequate for single supply processors, but no longer are sufficient to guarantee reliable operation of multiple supply processors. This white paper examines some of the challenges associated with resetting modern processors.
White Paper sponsored by Lattice
Using FPGAs for Trapezoidal Motor Control
Whether the need is for quieter blower fans in air conditioning systems, or greater efficiency under dynamically changing load conditions for an electric car drive-train, performance and cost goals for permanent magnet synchronous motor (PMSM or BLDC) controllers become more challenging by the day.
White Paper sponsored by Microsemi
Using LEDs as Light-Level Sensors and Emitters
Modulating LED power based on ambient light level increases battery life, a particularly helpful feature in a device where battery life is measured in days. Using a very simple circuit, Altera’s MAX II and MAX IIZ CPLDs can measure the analog light level of their environments and then drive an LED at a proportional analog intensity level. Controlling the LED intensity based on ambient light as demonstrated reduces LED energy usage by more than 47 percent without affecting appearance.
White Paper sponsored by Altera
Mixed-Signal Power Manager (MPM)
Actel's Mixed-signal Power Manager (MPM) enables designers to control and reduce power at the system level, offering fully-verified, timing-closed, proven-in-hardware power supervision and management capabilities, while utilizing Actel Fusion mixed-signal FPGA. Watch the short webcast to learn more.
Applying the Benefits of Network on a Chip Architecture to FPGA System Design
NoC interconnect architectures provide a number of significant advantages over traditional, non-NoC interconnects, such as allowing independent layer design and optimization. Altera's Qsys system integration tool, included with the Quartus® II software, generates a flexible FPGA-optimized NoC implementation automatically, based on the requirements of the application.
White Paper sponsored by Altera
Enabling High-Performance DSP with Arria V or Cyclone V Variable-Precision DSP Block
With many advanced applications in the market today requiring high and varying precisions, implementing complex digital signal processing (DSP) can be a challenge. Altera’s innovative variable-precision DSP blocks not only support high-performance signal processing, but also the unique precision requirements of your signal processing designs. Watch this webcast to find out more about the variable-precision DSP blocks in our 28-nm Arria® V and Cyclone® V FPGAs.
FPGA Configuration via Protocol
Altera’s new device configuration mode—configuration via protocol (CvP)—can be used with PCI Express® to configure the core fabric of Altera’s 28-nm Arria® V, Cyclone® V, and Stratix® V FPGAs. CvP can reduce product cost and board size, while simplifying the software usage model, and providing robust in-field system upgrade capability. In addition, the autonomous, embedded PCIe IP core helps ensure that designs meet PCIe power-up time requirements, irrespective of the FPGA core fabric configuration time, guaranteeing a wide range of interoperability with various PCIe-based computer platforms.
White Paper sponsored by Altera
Industry's First 28-nm High-End FPGA Running at 14.1 Gbps
Get an initial look at the industry’s first 28-nm high-end FPGA. In our Stratix® V FPGAs, you’ll get devices featuring: An industry-record 3.9 billion transistors, One million logic elements, Integrated transceivers with data rates up to 28 Gbps and an abundance of hard intellectual property (IP) blocks. Samples are shipping now. Watch this 3-minute video to see the progress of our silicon checkout process, as well as 14.1-Gbps transceiver performance.