industry news
Subscribe Now

Pentek Announces 8-Channel A/D Jade XMC Module for Defense and Radar Phased-Array Applications

  • Eight-channel, 250 MHz, 16-bit A/D XMC module with programmable multiband Digital Down Converters
  • Jade Architecture with Xilinx Kintex Ultrascale FPGA offers price, power and processing performance advantages
  • Navigator Design Suite compatible with Xilinx’s Plug-and-Play Vivado IP Integrator expedites development

UPPER SADDLE RIVER, NJ?January 23, 2017, Embedded Tech Trends Forum?Pentek, Inc., today introduced the newest member of the Jade™ family of high-performance data converter XMC modules based on the Xilinx Kintex Ultrascale FPGA. The Model 71131 is an eight-channel, 250 MHz XMC module featuring 16-bit A/Ds with programmable multiband digital down converters (DDCs).

The Model 71131 is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP. The eight channels make it especially beneficial for multi-channel phased array platforms in defense and weather radar applications where the cost per channel can be substantially reduced.

A/D Converter Stage

The front end accepts eight analog HF or IF inputs on front panel MMCX connectors with transformer coupling into four Texas Instruments ADS42LB69 dual 250 MHz, 16-bit A/D converters. The digital outputs are delivered into the Kintex UltraScale FPGA for signal-processing and routing to other module resources.

Performance IP Cores

The Model 71131 features eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the eight A/Ds or a test signal generator. Powerful linked-list DMA engines move the A/D data through the PCIe interface in a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary.

Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all eight DDCs or each of the eight A/Ds driving its own DDC.

Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as eight different output bandwidths. Decimations can be programmed from 2 to 32,768, delivering bandwidths ranging from 100 MHz down to a few kHz to best suit each application.

“Our customers are excited to take advantage of the Jade Architecture and our Navigator Design Suite,” said Bob Sgandurra, director of Product Development of Pentek. “Access to over 90 Pentek IP modules using the AXI interface has greatly eased their design effort, reducing cost and development time while eliminating worries about complex data converter interface issues.”

The Jade Architecture

The Pentek Jade Architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50% with equally impressive reductions in cost, power dissipation and weight. As the central feature of the Jade Architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. A 5 GB bank of DDR4 SDRAM is available to the FPGA for custom applications. The Gen.3 x8 PCIe link can sustain 6.4 GB/s data transfers to system memory. Eight additional gigabit serial lanes and LVDS general purpose I/O lines are available for custom solutions.

Navigator Design Suite for Streamlined IP Development

Pentek’s Navigator™ Design Suite was designed from the ground up to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite® providing an unparalleled plug-and-play solution to the complex task of IP and control software creation and compatibility. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design. The Navigator BSP is available for Windows and Linux operating systems.

Pre-Configured SPARK System Ready for Immediate Use

With a Pentek 8266 SPARK® PC, 8264 SPARK 6U VPX, or 8267 SPARK 3U VPX development system, work can begin immediately on applications. A SPARK system saves engineers time and expense associated with building and testing a development system and ensures optimum performance of Pentek boards. SPARK development systems are ready for immediate operation with software and hardware installed. In many applications, the SPARK development system can become the final deployed application platform.

Form Factors

The Model 71131 XMC module is designed to operate with a wide range of carrier boards in PCIe, 3U & 6U VPX, AMC, and 3U & 6U CompactPCI form factors, with versions for both commercial and rugged environments.

Pricing and Availability

Designed for air-cooled, conduction-cooled, and rugged operating environments, the Model 71131 XMC module with 5 GB of DDR4 SDRAM starts at $13,495 USD. Additional FPGA options are available. Delivery is 8 to 10 weeks ARO.

The Navigator Design Suite consists of two packages. The Navigator BSP is $2,500 USD and the Navigator FDK is $3,500 USD.

Leave a Reply

featured blogs
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...
Apr 16, 2024
Learn what IR Drop is, explore the chip design tools and techniques involved in power network analysis, and see how it accelerates the IC design flow.The post Leveraging Early Power Network Analysis to Accelerate Chip Design appeared first on Chip Design....
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

PIC® and AVR® Microcontrollers Enable Low-Power Applications
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Amelia Dalton and Marc McComb from Microchip explore how Microchip’s PIC® and AVR® MCUs are a game changer when it comes to low power embedded designs. They investigate the benefits that the flexible signal routing, core independent peripherals, and Analog Peripheral Manager (APM) bring to modern embedded designs and how these microcontroller families can help you avoid a variety of pitfalls in your next design.
Jan 15, 2024
13,210 views