Freiburg, Germany, and ALAMEDA, CALIF. –– May 1, 2014 –– Electronic Design Automation (EDA) component software leaders Concept Engineering and Verific Design Automation today announced immediate availability of a connectivity package that links Concept Engineering’s NlviewTM schematic generator and visualization engine with Verific’s netlist database.
VVDI-Link gives Nlview, used within EDA tools to automatically create and visualize schematics for different levels of electronic circuits, direct access to the Verific database of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers. It is available from Concept Engineering as part of its Nlview family at no additional charge to existing customers.
“Concept Engineering and Verific have worked together since 2003 and continue to look for ways that will improve a designer’s productivity,” says Michiel Ligthart, Verific’s president and chief operating officer. “While a connectivity package may seem trivial, it’s actually a critical link.”
The same technology is deployed in Concept Engineering’s RTLvision® PRO tool, a powerful, easy-to-use register transfer level (RTL) viewer and debugger that combines Verilog, VHDL and SystemVerilog viewers in one integrated debugging cockpit.
“Software design teams rely on high-quality software components, such as automatic schematic generators and language parsers, which is why it was important to link our tools together,” comments Gerhard Angst, Concept Engineering’s chief executive officer and president. “Our new VVDI-Link package makes it easy to create innovative debugging cockpits for EDA tools.”
Concept Engineering’s Nlview provides automatic generation of schematic diagrams for different levels of electronic circuits, including transistor, gate, RTL, block and system. A fine granularity of user preferences can be mixed with machine computed “beauty” for the best human-readable diagrams. Interactive circuit exploration is supported by incremental schematic generation and navigation technology. Nlview provides a set of application programming interfaces (APIs) and interfaces for different GUI platforms.
Verific’s software is the front end to a variety of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl APIs. Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
Concept Engineering and Verific at DAC
Concept Engineering and Verific will exhibit at the 51st Design Automation Conference (DAC) in Booths #1201 and #1909, respectively, Monday, June 2, through Wednesday, June 4, from 9 a.m. until 6 p.m. at the Moscone Center in San Francisco.
The DAC website is found at: www.dac.com.
About Concept Engineering
Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, circuit characterization, circuit optimization, test automation and physical design tools. The company’s customers are primarily EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information, visit: www.concept.de.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.
