industry news
Subscribe Now

Imec solves metallization issues in advanced interconnects for the sub-1X technology node

San Francisco (USA) – July 2, 2013 – Imec has developed a Manganese (Mn)-based self-formed barrier (SFB) process that significantly improves Resistance Capacitance (RC) performance, via resistance and reliability in advanced interconnects. It provides excellent adhesion, film conformality, intrinsic barrier property and reduced line resistance. This technology paves the way towards interconnect Cu metallization into the 7nm node and beyond.

With continuous interconnect scaling, the wire resistance per unit length increases, which has a detrimental impact on the device performance (RC). Moreover, when reducing the dimensions with conventional barrier layers, an increased loss of copper (Cu) cross sectional area is observed, resulting in high resistance and decreased interconnect lifetime (electro-migration and time dependent dielectric breakdown – EM and TDDB). To overcome these interconnect metallization issues when scaling beyond the 1X technology node, imec’s R&D program on advanced interconnect technology explores new barrier and seed materials as well as novel deposition and filling techniques. The Mn-based SFB was demonstrated to be an attractive candidate for future interconnect technology.  At module level, Mn-based SFB resulted in a 40% increase in RC benefits at 40nm half pitch compared to conventional barrier and good lifetime performance (comparable to TaN/Ta reference).

These results were achieved in cooperation with imec’s key partners in its core CMOS programs Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.

Imec exhibits at SEMICON West, July 9-11, 2013. To learn more about imec, please visit booth 1741, South hall.

Leave a Reply

featured blogs
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Achieving High Power Density with IGBT and SiC Power Modules
Sponsored by Mouser Electronics and Infineon
Recent trends in the inverter market have made high power density, scalability, and ease of assembly more important than ever before. In this episode of Chalk Talk, Amelia Dalton and Abraham Markose from Infineon examine how Easy & Econo power modules from Infineon can help solve common inverter design requirements. They explore the benefits and construction of these modules and how you can take advantage of them in your next design.
May 19, 2023
36,785 views