Cadence Launches Innovus
It’s a familiar tale of woe: new silicon process nodes are creating an extreme burden for design tools.
When I say, “familiar,” it’s not just because everyone is bemoaning the current state of affairs, what with FinFETs and multiple patterning and other new features creating innumerable vexations. No, it seems that this happens after every few advances: the improvements made to nullify the last set of hurdles run out of steam in the face of the latest set of new hurdles. And so tools get rolled again.
The product of the tools – a correct mask set – hasn’t changed; the ways we get to that mask set have changed over and over. And continue to do so.
Taming the Wild West of EDA Design with OneSpin
This week we’re saddling up and taking a ride into the Wild West, where the days are long and the code is even longer. We’re talking about the rough and tumble, SystemC slingin’, HLS wranglin’ assertion-based formal verification. Dave Kelf (OneSpin Solutions) rides with us across the dusty EDA plains of RTL design where we unveil why RTL (and above) is called the Wild West of Design, who exactly is playing sheriff in these here parts, and how design and verification at the RTL level can be corralled once and for all. Also this week, we address the most recent rumors surrounding the Intel/Altera buyout deal and investigate the newest (and coolest) smartwatch this side of the Mississippi - an Enigma machine for your wrist!
Synopsys EV Processor for Games, Security, and Everything
Politicians used to argue about “the vision thing,” a borderline unintelligible swipe at opponents who didn’t share their view of the big picture. As a company, Synopsys may not be very political, but it’s definitely on board with the vision thing.
Embedded vision – that is, adding real-time image recognition to embedded systems – used to be a high-end, pie-in-the-sky kind of feature. Cheap systems couldn’t do image recognition, could they? They don’t have the processing power. And anyway, what would you do with it? Why does a thermostat need to recognize my face?
Flex Logix Debuts FPGA Cores for IC Designers
Kato, Robin, Watson, Tonto, Spock, Barney, Hutch, Higgins, FPGAs - everyone knows the importance of a top-notch sidekick. We’ve seen FPGAs teamed up with countless heroes, parked next to just about every type of device you can imagine. And FPGAs are steadfast in the fulfillment of their duties - bridging the logic, driving the interfaces, accelerating the processing, scaling the video, integrating the peripherals - no task is too unglamorous for the hard-working FPGA - and it often manages several of these at once.
Today, if you’re designing a custom chip, chances are you’ve already considered putting an FPGA next to it. And that’s before your custom design is even done. There are just too many variables in a new design, and you have to assume that you won’t have them all nailed down before you tape out. There may be some standards that aren’t solidified yet (and you certainly don’t want to wait for standards committees to finish their seemingly-endless deliberation before you proceed with your design).
New Interchanges for Data Centers
Picture the huge datacenters run by Google and Facebook and their ilk. Imagine that, as big as they are, each of those datacenters serves only one company.
Now picture an Internet-of-Things (IoT) world where everything is connected, with data flying hither and yon, and with some non-trivial part of that data making its way to new datacenters built to handle the additional load. That could mean incredible distributed computing resources.
Even today, you may think of all the traffic that the internet sends to Google and Facebook – nothing to sneeze at, and yet it’s only part of the overall traffic they have to handle internally. For redundancy, performance, and scalability reasons, data is replicated and cached and optimized constantly, resulting in huge amounts of intra-farm traffic that never escapes the building.
Molex and the Connectors of Tomorrow
They’re super important, and every design needs them, but let’s face it - connectors have gotten a bad rap for being a bit boring. In this week’s Fish Fry, we explore into the multi-faceted world of today’s connectors and cables where signal integrity rules the roost and multi-gigbit SerDes is king. My guest is Joe Dambach (Molex) and we discuss how Molex is using correlated models to solve today’s signal integrity and high-speed serial design challenges, how datacenters are changing the face of connector and cable technology, and why connectors and cables aren’t as boring as we once thought they were. Also this week, we look into this week’s hottest rumor swirling around the EE halls: Will Intel buy Altera?