Hard IP, eFPGAs and the Moore's Law Bottleneck
What if you could have your FPGA cake and eat it too? What if you could modify your RTL post-production and have several variations of an algorithm on the same chip? Let me introduce you to eFPGAs. Yoan Dupret from Menta joins Fish Fry this week to discuss the details of Menta’s eFPGAs, the benefits of embedding field programmable gate array fabric as an IP core, and what process geometries are supported by Menta's eFPGAs. Also this week, Fish Fry welcomes Ramy Iskander from Intento. Ramy and I chat about the challenges of tools in the analog world and how Intento is working on fixing the “Moore’s Law Bottleneck”.
Oracle’s Newest SPARC S7 Processor Makes More of Less
“The older I get, the faster I was.” – popular racing driver’s adage
Some engineering designs, like some felons, are just born bad. Others start out bad but eventually turn themselves around and come out fine. And some become spectacular successes, despite their inauspicious beginnings.
The Ever-elusive Perfect Engineering Environment
Let’s make one thing perfectly clear right off the bat. Engineering is not an assembly line.
Life would be much simpler and cleaner if we could just start with a pile of widgets that needed to be engineered, quickly and methodically remove and engineer each one, and smoothly transfer it to the neat and tidy “engineered” stack. If one engineer could engineer 5 widgets per hour and we had 8 work hours per day, that would be forty widgets per engineer-day of output. A team of ten engineers could therefore engineer four hundred widgets per day, or two thousand widgets in a week. Project scheduling would be a dream. If we were a thousand widgets behind schedule, we’d know exactly how many hours of engineering overtime we’d need to ask for to get back on track.
SeaScape for SeaHawk and Other Tools to Come
Hey there! Well it looks like you’ve just launched a full-chip analysis of your project, so… well, you’re gonna have some time on your hands. While you’re awaiting results, let’s talk about some ways that we might reduce that spare time (assuming that you’re not counting on that spare time for getting other things done – or just relaxing).
EDA has always struggled with run times. And that’s because EDA tools have a huge job, taking big designs (some might not seem big today, but in their day, they were) and identifying problems or optimizing or whatever in a timeframe that seems long when it comes to sitting around waiting for results, but is still far faster – and more accurate – than a human (or a bunch of humans) could do.
Lynx Design System Bridges the Breach Between Chip Capacity and Engineering Ability
He’s been up all night. The row of green and white soda cans marks the passage of time in a steady line across his desk. Everyone else has gone home for the day, but he’s still here, clicking "send to voicemail" on his Mom's call. Nothing, including days without sleep, is going to distract him from his looming deadline. We’ve all been there at least once or twice in our career - burning the engineering candle at both ends, struggling to do more with less. In this week’s Fish Fry, we take a closer look at the “Productivity Gap” that plagues all of us at one time or another. Andy Potemski (Synopsys) and I discuss the void between the enormous capacity of today's chips and our ability to get the design job done. We discuss how the Lynx Design System can make our system design lives a whole lot easier and why the "Productivity Gap" is more prevalent now than ever before.
IoT Takes People Out of the Loop
The imminent IoT is the final phase of a computing revolution that began decades ago.
First, it was all about processor speed. From our puny 8-bit 1MHz microprocessors to today’s 64-bit multi-core multi-gigahertz behemoths, the pursuit of MIPS and FLOPS led us from machines that could barely run the most rudimentary programs to multiprocessing beasts that can crunch data at unimaginable speeds. Over time, however, processor performance gradually faded from the spotlight. Now, the incremental capability we gain with a doubling of processor speed is comparatively insignificant, and the focus in processor design has switched from raw performance to power efficiency.