EEJournal

fish fry
Subscribe Now
June 9, 2016

DAC to the Future

IoT, Debug, and Verification at DAC 2016
by Amelia Dalton

It’s that time again! This week’s Fish Fry is coming to y’all from the great state of Texas and the heart of the electronic design ecosystem: the Design Automation Conference in Austin. We’re laying out a virtual chuckwagon of DAC bounty. For our first course, we’ll fry up some IP with David Rose of UltraSoC. Next, dig in to delicious debug automation with Daniel Hansson of Verifyter. And finally, you can feast on aromatic ASIC/FPGA verification with Louie DeLuna and Krzysztof Szczur of Aldec. You’ll also want to stick around for our take on the entertaining bits and bobs at this year’s conference and a special News You May Have Missed.

 

 

Download this episode (right click and save)

Links for June 10, 2016

More information about the 2016 Design Automation Conference

More information about UltraSoC

More information about Verifyter

More information about Aldec

Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC Designs

Leave a Reply

featured blogs
One Robotic Step Closer to Humanoid Robots in the Home
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
More from Max's Cool Beans...
Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....
More from Synopsys...
Rapid Prototyping of Analog Circuits with Verilog-A Modeling
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...
More from Cadence...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Introducing QSPICE™ Analog & Mixed-Signal Simulator
Sponsored by Mouser Electronics and Qorvo
In this episode of Chalk Talk, Amelia Dalton and Mike Engelhardt from Qorvo investigate the benefits of QSPICE™ - Qorvo’s Analog & Mixed-Signal Simulator. They also explore how you can get started using this simulator, the supporting assets available for QSPICE, and why this free analog and mixed-signal simulator is a transformational tool for power designers.
Click here for more information about Qorvo QSPICE™ Simulator
Mar 5, 2024
4,900 views