“Bifurcate” is a word you don’t get to use very often. Yet it’s a familiar concept in our industry. Mobile operating systems have bifurcated into the choice between Android and iOS. On the desktop, it’s Windows or MacOS. Verizon or AT&T. Home Depot or Lowes. ARM or x86.
In all of these cases, the big pie chart is pretty much equally divided between two major players, with a thin sliver of “other.” In the desktop environment, the “other” slice of the pie includes Linux: it’s there, but it’s not really used by normal people and doesn’t really compete on the same footing as Windows or MacOS. The mobile OS market includes BlackBerry and Windows Phone, among others, but in the big banquet of life they’re relegated to the kids’ table.
In microprocessors, it’s beginning to look like a two-horse race as well. You use x86 chips if you need PC or Windows compatibility, and you use ARM for everything else. To be sure, there are dozens of “other” microprocessor choices out there, but why bother!
Well, because those “other” vendors may give you something the two big players don’t, that’s why. Even though the high-end 32/64-bit CPU market has bifurcated, all those other architectures filling in the gaps deserve a look, too. And chief among the “other” CPU families is MIPS.
MIPS has always been perceived as the arch-rival to ARM, and with some justification. Under the hood, the two architectures are vaguely similar, are about the same age, and are based on similar RISC principles. They’re both licensed as IP cores to third-party vendors, which means you can make your own ARM- or MIPS-based processor if you’re rich, or buy off-the-shelf components if you’re not.
ARM has earned the reputation as the power-efficiency leader – the CPU you want when battery life matters – but that status is largely undeserved. Lots of other CPUs, including MIPS, are at least as good at saving energy. (Firm numbers are hard to come by because we’re talking about IP design files, not hard silicon.) Still, MIPS is a worthy opponent and puts up a good fight.
Which brings us to this week’s news: there’s a brand new member in the MIPS product family. It’s called the I6400, and it fits right into the middle of the brand’s high-end embedded processor lineup. The initial “I” means it’s a midrange CPU core (as opposed to the low-end M-series or the high-end P-series). But “midrange” may be a misnomer here because the 6400 in the name means it’s a 64-bit design.
If you think of all CPU cores in terms of ARM nomenclature, think ARMv8 – in other words, the 64-bit version, like a Cortex-A53 or –A57. This is MIPS’s 64-bit product for volume production, slotted underneath the P5600 we saw late last year.
But wait – isn’t the P5600 a 32-bit CPU, while the new I6400 is a 64-bit design? Yup, but that’s how Imagination Technologies (MIPS’s corporate overlord) wants to play it. Even though the I6400 is “bigger” in that sense, it’s also moderated for modest die size and sensible power consumption. As the company’s newest CPU core, it’s also the one leading the charge into full 64-bittedness. A new era has arrived.
The new I6400 also boasts simultaneous multithreading, something MIPS has offered on some of its cores before – but which ARM doesn’t offer in any configuration. MIPS staked out multithreading as a differentiator a long time ago, but it’s a path that ARM’s engineers have consistently chosen not to follow, despite earlier hints that ARMv8 might go that route.
The I6400 also offers hardware virtualization, supporting up to 15 “guest” operating systems or applications. Virtualization is becoming a big deal as embedded systems get bigger and developers mix real-time operating systems along with friendlier operating systems that control the user interface or that support third-party applications. The hardware support helps hypervisors keep things separate.
And, the I6400 comes with 128-bit SIMD, both for integers and for floating-point data. SIMD is also something MIPS has offered for a while, but this is its first appearance in a relatively affordable CPU core. Expect this to be a standard feature from now on.
In a bit of a break from tradition, the I6400 isn’t actually a specific processor implementation, like a Core i7-4770 or an ARM7TDMI. Instead, “I6400” is a sort of placeholder name, the blanket term for a range of individual spinoff designs with various numbers of clustered CPU cores, different cache sizes, and so on. Since licensing CPU cores isn’t really a retail business (“Hi, I’d like $1.2 million dollars’ worth of CPU, please. To go.”), there’s no need to announce or advertise individual implementations. Interested customers know how to contact Imagination Technologies and get the inside scoop on what’s available. Everyone else is left to guess the details.
Getting back to the 64-bit thing, the I6400 can run both 64-bit code and 32-bit binaries at the same time. There’s no mode-switching involved, nor any separate instruction set. Earlier MIPS cores (and earlier ARM cores) used to segregate their “native” and “compressed” ISAs, but that old-school approach has been replaced by a newer, merged instruction set.
It’s a great idea, but it comes at a cost. In the case of I6400 (and presumably, future 64-bit MIPS cores as well), it means that the company had to do some surgery on the opcode map. Translation: they removed some existing instructions and reassigned the opcodes. That means I6400 isn’t strictly binary compatible with other MIPS processors. There simply wasn’t room in the old opcode map to add the new SIMD or virtualization instructions without cutting something out first; hence the break with tradition – and compatibility.
In its defense, the company says that the instructions it sacrificed were infrequently used anyway, so few programmers will know the difference. They were just an outgrowth of over-exuberant ISA growth in earlier years, and they needed to be brought back to reality. Ironic, indeed, that a “reduced instruction-set computer” would have too many instructions. At any rate, programmers can simply recompile their code with an up-to-date compiler, and any jettisoned opcodes will be replaced with their modern equivalents. Nine times out of ten, there won’t be a need for changes at all. And if you can’t recompile, there’s always emulation, patching, or traps.
The I6400 sets a new high point in the MIPS tower of CPU designs. It’s a rational 64-bit design with floating-point, SIMD, power management, and multithreading, and it will be the genesis for a range of spinoff implementations. The multithreading, in particular, sets it apart from its rivals from Cambridge. Depending on the benchmark you use, enabling two-way multithreading improves performance by 30% to 50% over the same code in single-threaded mode. Turn on four-way multithreading, and performance may improve even more. It’s the classic performance-versus-area tradeoff that all chip designers face, and it’s a knob that MIPS lets you control but that ARM doesn’t offer. For now, it’s enough to set MIPS apart from ARM. A bifurcation, you might say.
