Years ago I saw a television wildlife programme about penguins. One image that has remained in my mind was that of the hungry penguins clustering on the edge of the ice, needing to go to catch fish, but each frightened to be the first in, as there might be an equally hungry leopard seal wanting a meal of penguin. Eventually, a penguin gets pushed in by his friends. If he survives, the rest then jump in after him.

This image has always recurred to me as chip manufacturers approach the next wafer size increase. They all want to get the benefits of a larger size wafer, but they are frightened to be the first to use the new equipment that will be needed. Eventually, someone makes the leap, and then the rest pour in.

However, this image isn’t relevant to the move to 450mm wafers. For a start, there are only three penguins at the edge of the ice. There are other penguins in the game, but they are standing well away from the edge, and some of them have said they are not hungry enough to even begin to think about going into the water.

Firstly – who are the three penguins? According to Malcolm Penn, CEO of Future Horizons, analysts charged by the European Commission with a range of 450mm activities, including producing a regular newsletter on what is happening, the three penguins are Intel, TSMC, and Samsung. And they are already dipping their flippers into the water by each making an investment in ASML, the Netherlands-based manufacturer of the lithography equipment that is at the heart of wafer processing. Intel has bought 15% of the company for $3.1 billion and has put a further billion dollars into ASML’s R&D. TSMC has 5% for $1.03 billion and $345 million in R&D, and Samsung 3% for $630 million and a further $345 million in R&D. This serious money is to ensure that ASML has the funds to develop the kit and give the investors first dibs on the supply of equipment.

Before going any further – why do manufacturers want to move to larger wafers? The answer is simple – they will get cheaper die. According to Future Horizons (whose figures and views I am going to quote from, freely – if this were an academic paper, many of the statements about 450mm progress would be footnoted to a Future Horizons’ paper or presentation. I am of course responsible for any mistakes or misunderstandings.) As I was saying – according to Future Horizons, a 450mm fab costing $10 billion is the equivalent of 2.25 300mm fabs. What with fewer staff needed and more die per wafer, this will lead to reduction in die cost of around 28%. Of course, process developments also make die smaller and reduce the cost.

One issue is that at the same time as the industry is looking at 450mm, it is also looking at new and smaller process nodes, and there is a general agreement that future nodes will require the use of extreme ultra-violet lithography (EULV). This is another area that will require significant investment and where ASML is a leader.  But while there is no reason for the move to 450mm to be tied to a specific new process node, it seems to be fairly widely accepted that this is likely to happen. (But see the appendix, below, on what a process might really mean.)

However, any work on smaller nodes can be used, not just for 450mm, but can be part of an advanced 300mm line if 450 take longer to arrive than planned. After all, 300mm lines being constructed today are very different from those built when the wafers were first introduced.

There are two centres working on 450mm, both as part of collaborative ventures. In the USA there is the G450C – Global 450 Consortium. This consists of Intel, IBM, GLOBALFOUNDRIES, TSMC, Samsung, and Nikon working together at State University of New York’s College of Nanoscale Science and Engineering with the backing of the State of New York. Penn says that 450mm must be serious: “… let’s be honest, when was the last time this lot agreed to work together?”

In Europe, the project is Enable450, centred on the Belgian research organisation, IMEC, with a long list of equipment and materials (E&M) companies, research organisations, and Intel. Most of the semiconductor manufacturers have a presence in IMEC on a wide range of projects outside the work on 450mm. Also part of the acronym soup is EEMI450, a consortium of European companies working on promoting 450mm and developing standards for it. This is funded by ENIAC. (See Europe Takes on the World.)

All this co-operation is in marked contrast to the introduction of 300mm wafers, where each manufacturing company did its own work, assembling its own collection of manufacturing equipment. This is, in part, a reflection of the increasing complexity and cost of process development, in part a reflection of the shrinking pool of E&M companies, and, in Europe, a result of the determination by Commissioner Neelie Kroes that Europe should be a major player in chip manufacture, with 20% of the world’s output, which in turn requires a strong support industry. The three major European Semiconductor manufacturers’ attitude to 450mm is summarised by Penn as “Non/No, Nee & Nein” although the recent report to Kroes by the European Leaders Group on how to achieve her goal may have softened this attitude slightly.

The initial feeling in G450C seems to have been that the consortium would get on with the work, telling the E&M companies just enough for them to make progress and otherwise ignore the rest of the world. This has changed, mainly due to the work of Bernie Capraro of Intel Ireland, according to Penn. Today G450C recognizes that Europe outside ASML can be, and is, a major contributor to 450mm development. This has already resulted in information sharing and in joint performance metrics for manufacturing equipment; equipment manufacturers will know that they have to meet only one set of metrics.

Europe has also created another initiative: Bridge450. This has the objective of helping SMEs (Small and Medium Enterprises) in Europe to communicate with semiconductor companies, particularly those in Asia, in order to understand their requirements, other than lithography, for 450mm. SMEs are already pooling their information, and the first round of meetings in Asia is planned for May, with US meetings planned for June.

This is all good stuff, but when can we expect to see 450 manufacturing become mainstream?  Penn originally predicted pilot lines in 2015, with the production ramp starting in 2018. IMEC is still on schedule to meet 2015 for its pilot line, but it is less clear what is happening with Albany and Intel pilots. Of the penguins, Intel appears to have put a hold on fitting out new plants. TSMC has not made a formal announcement for some time, and Samsung is keeping quiet. This suggests that the beginning of the production ramp is slipping past 2018. It also creates uncertainties for the E&M companies.

It is possible to create graphs, to extrapolate from past experience, and to even guess what is going to happen in the semiconductor industry. Yet it still pulls surprises. The fact that there is so much co-operation going on around 450mm is a positive sign. But, apart from our three penguins, how many companies are going to make the transition? Is this going to be another trigger for more companies to go “Fab-lite” or even fab-less?  IBM is rumoured to be looking at ways of divesting its semiconductor business. The PC business, traditionally a driver for Intel, has stopped growing, and consumer products appear to continue to have a decreasing life-cycle, far faster than the traditional chip life-cycle.

All of this suggests that we might be at another inflexion point for semiconductors. Penn also points out that Makimoto’s wave is due to make another inflexion in 2017. So something new may be coming. He feels that this might be some new form of making very large devices customisable, perhaps through programmability.

Something is going to have to change soon, so hang on. As the semi manufacturing business has always been, it may be bumpy ahead, but it is likely to be exciting.

Appendix – what is a process node?

Malcolm Penn argues that the node dimension has, since 90nm, ceased to be an accurate measure of the dimensions of the features on a die, but rather has become part of the marketers’ hype, “Mine is smaller than yours.”

FinFET, he feels, has given this a new twist. What are billed as 14nm/16nm “are simply the planar 20nm layouts with a decent (vertical) transistor in the same space as the (leaky) planar device”.

He also has a table of how he would describe what are billed as 14nm process nodes

Intel            16nm
Samsung     18nm
TSMC          19nm
GloFo          20nm
STM            21nm

From this, he suggests, you treat any manufacturer’s node figures with a shovel-load of salt. After all you don’t buy a device just because it is fabbed in 16nm or 14nm, do you?