July 7, 2011

Controlling Power During IC Production Test

by Ron Press, Arik Krantz, Asher Berkovitz, Cynthia Hao, and Giri Podichetty

Many of today’s integrated-circuits (ICs) are designed to operate in low-power modes to accommodate greater analog-digital integration, faster operating frequencies, and battery-powered applications. During semiconductor manufacturing test, the majority of logic is often activated concurrently to facilitate detection of many faults within a small set of patterns to reduce test time. Activating all the logic at once uses more power than these low-power devices were designed to function under, which can cause them to fail or burn out during test.

This divergence in functional power versus test power means that the test application has to allow power thresholds to be set so that overstressing devices beyond the functional design and operation is avoided.

During manufacturing test, we saw these types of power-related issues while working on a pilot project with C90 nm technology and C90 nm TFS (thin film storage) processes. This article describes how we used low power test to solve these issues and the results. We also used these techniques on a StarCore DSP design using 45 nm technology operating at 1 GHz.

Scan tests were failing at lower frequencies than functional patterns on the previous-generation 90-nm DSP device [1]. Silicon measurements demonstrated that scan tests were causing a 22% power droop. Data at the problem flop was not effectively clocked because of the scan test power droop; however, the functional pattern had negligible droop and properly captured the data at that flop. Although this case was shown to be caused by a packaging issue, it is important to note the difference between scan and functional test results. A second effect of clock stretching was also found to be more pronounced during scan tests. The power level reported by the ATPG tools was compared to the power simulation results and was found to have a strong correlation.

We discovered in silicon debug on the next-generation device that it suffered from high test power that caused high IR drop. Consequently, the device was inhibited from reaching the target test frequency. Devices were failing at 20% lower frequency than expected because of this power-induced IR drop. We averted a potential yield issue by using the following design-for-test (DFT) methods.

Best Strategies to Reduce Test Power

We used these low-power DFT and automatic test-pattern generation (ATPG) techniques to effectively set a threshold for power during test.

Low-Power ATPG

Each scan test pattern has two main modes: shift and capture. Scan load-shifts values in through the scan chains to set up a desired state or to unload captured values. Once the scan chains are loaded, the circuit is placed in a normal operational mode and the clocks are applied to capture values through the combinational logic.

Special low-power features exist for both shift and capture in ATPG tools such as Tessent TestKompress. Power management operates in a very different manner for shift and capture and is controlled independently.

Low-Power Shift

A fundamental power issue with scan test is that it normally activates all flops and shift-loads values into them in parallel. This could be a dramatic departure from the activity and power expected in the design’s functional operation.

The majority of devices that are scan-tested today use embedded compression technology to enable many pattern types to be applied in a fraction of the time it would take using traditional scan. Embedded deterministic test (EDT) technology only affects the scan-shift load/unload, making it roughly 100 times more efficient than traditional scan [2]. The principle behind the efficiency improvement is that only a small percent of scan cell values can be usefully defined in what is called specified bits. Other bits are randomly filled. In the case of EDT, the random filling is produced by on-chip decompression logic.

EDT technology includes a low-power shift option that takes advantage of specified bits being a small population of scan cell bits for any particular pattern [3]. A threshold can be set such that during pattern generation only a percent of scan chains will shift in values for that pattern. Other scan chains will hold a steady state. EDT ATPG decides which chains to allow to propagate values based on specified bits necessary for each pattern and the low-power threshold setting. As a result, the state transitions can be reduced from 50% normal shift to a set value.

Low-Power Capture

ATPG tools can take advantage of existing gated clock to control the capture power. Similar to low-power shift, a threshold is set and specified bits determined. For capture, the fault detection points are determined. There will be a lot of additional fault detection due to random values being captured into scan cells from faults that were not targeted throughout the circuit. The state transitions caused by the capture can be controlled by using existing gated clock in the design. If a gated clock cone of logic does not need to be active to capture and detect a targeted fault, then the ATPG tool will automatically turn it off as necessary to meet the defined capture threshold.

Reporting ATPG Power

An important aspect of the low-power ATPG features is the ability to report and analyze shift and capture power for existing patterns. This enabled us to determine if specific patterns that are failing happen to have higher power than other patterns. Knowing which patterns have higher power or high power within a specific block is very useful when troubleshooting. Also the high power patterns can be sorted and removed if desired. State transitions is a common metric that is accepted as a good correlation with device power. A random set of values captured into a set of flops will have roughly 50% state transitions. This is the common situation when shifting into scan chains. Both shift and capture reporting from the ATPG tools include state transitions. In addition, capture reporting includes a weighted switching activity (WSA) metric. WSA includes the fan-out region of each state element in the calculation.

Results on the C90 Device

We used EDT compression technology in the 90-nm design that had more than 50,000 flip flops with the low-power shift feature. The configuration of the device consisted of one EDT block for the circuit, 12 scan channels, 565 internal scan chains for 58K scan flops, and 12 clock domains.

Experiments on this project demonstrated that test coverage was maintained when running low-power shift and capture. There was a pattern increase but comparing the C90 design that had normal EDT and a version with low-power EDT (see Figure 1), it was not significant. Three cases of the low power EDT design are shown in Figure 1:

fig1.png

Figure 1: C90 coverage and pattern count using low-power EDT.

 

  • Low-power EDT with both shift and capture power enabled.
  • Low-power EDT with only low-power shift activated and capture is normal.
  • Low-power EDT but with the low-power features disabled.

Test coverage was maintained in all cases. When low-power EDT was added to a design but not enabled, then all results were the same as the EDT design without any low-power feature. Because low-power EDT disables various scan chains on a pattern-by-pattern basis, more patterns are required to reach the full coverage. Thus, the low-power shift and capture case requires more patterns than without these features activated.

Figure 2 shows a significant reduction of scan load, unload, and capture power when using low-power EDT.

fig2.png

Figure 2: C90 power levels using low-power EDT.


Test Power Correlation to Power Analysis Tools

We compared the capture power reported by the ATPG tool and that reported by a power analysis tool. The average power of the whole chip for a few patterns is shown in Table 1. Peak power was not included in the comparison. Values in Table 1 were reported from the ATPG tool. The WSA shows the average power across all capture cycles and the power from the peak capture cycle in parentheses. Note that pattern 19 and 351 show the max and minimum capture power reported by the ATPG tool. 

Table 1: C90 ATPG reported power for several patterns.

table1.png

Comparing the patterns with a larger variance shows very good correlation with the power analysis tool. Looking at a standard correlation function [4]:

Screen_shot_2011-07-04_at_2.38.48_PM.png

shows an excellent correlation between power analysis and ATPG estimate. The three patterns shown in Figure 3 produce a correlation of 0.998. Note that patterns with very small variation in reported power do not show a good correlation with power analysis tools. Thus, it appears that there is excellent correlation between power analysis and ATPG tool power reporting for patterns that have high or low power.

fig3.png

Figure 3: Capture WSA cycle power (power metrics) correlation to power analysis simulation
(power number).


Results on the C45 DSP Device

We also used these techniques on the 45 nm DSP device. EDT compression technology, including the low-power shift control feature, was roughly 1% of the design area..

We used a power analysis tool to estimate di/dt with the design’s timing SDF information. Three waveforms were calculated as shown in Figure 4. The smoker waveform is based on functional cycles running all the MAC units inside the ALU with reads/writes to memory. This represents a high-power functional mode. A standard scan pattern capture waveform is labeled as DFT STD and has significant di/dt impact. EDT with the low-power feature enabled us to produce capture power set to less than 20% is shown as DFT WSA <20. Results show a significant improvement in di/dt for the low-power patterns.

fig4.png

Figure 4: Improved scan di/dt with low-power EDT.


Several similar graphs were verified against tester measurements and showed a correlation around 5% between these estimates and silicon behavior. Thus, we had high confidence in the low power feature and results.

Low-power ATPG is a necessity for many semiconductor devices today. Too much power during test mode can lead to incorrect frequency binning. Functional power levels will continue to be reduced and force tighter requirements for low-power production test. Fortunately, low-power ATPG techniques can be used to effectively set the threshold for power during test In addition to the techniques described here, new low-power test pattern reporting features are available for higher resolution analysis and manipulation that allow more precise pinpointing of power issues.

References

  1. S. Sde-Paz & E. Salomon, “Frequency and Power Correlation between At-Speed Scan and Functional Tests,” Proc. Int’l Test Conf. (ITC 08), IEEE Press, 2008.
  2. J. Rajski, et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. Int’l Test Conf. (ITC 02), IEEE Press, 2002, pp. 301-310.
  3. D. Czysz, et al., “Low Power Scan Shift and Capture in the EDT Environment,” Proc. Int’l Test Conf. (ITC 08), IEEE Press, 2008.
  4. Trochim, William M. The Research Methods Knowledge Base, 2nd Edition. Internet WWW page, at URL: http://www.socialresearchmethods.net/kb/ (version current as of October 20, 2006).

 

SIDEBAR

Traditional Methods for Controlling Test Power

Reduce Clock Speed

Reducing the clock frequency allows power to dissipate and reduces the heating and average power. However, reducing the frequency could exacerbate a problem with di/dt instantaneous power because the circuit will settle more between the lower frequency clock pulses.

Clock Skewing

One of the early approaches to lowering power during test was to skew various clocks in the design such that they rise at different points within the cycle. Thus, di/dt would be reduced depending on how many clocks exist where skew could be manipulated. The drawback with this technique is that it is highly dependent on the clock design, does not help with average power, and is circuit dependent. Some devices would likely still have localized di/dt.

Test Scheduling

Another early approach to lowering power during test is to test the device in hierarchical partitions; one at a time. Consequently, many blocks could be in an idle mode while test is sequenced through the various blocks. Average power would be significantly reduced. Unfortunately, there is still the opportunity for localized power issues to occur within individual blocks.

Manage Power as Part of Pattern Generation

The best solution to reduce the instantaneous di/dt power as well as average power is to use test logic and automated test pattern program generation (ATPG). Features were recently added to ATPG tools such that activity levels could be measured and controlled. As a result, both di/dt and average power could be flexible and managed when generating test patterns. These techniques also allow the power threshold to be adjusted based on first silicon results.


About the Authors 

Ron Press is the technical marketing manager for Mentor Graphics Silicon Test Solutions. He is also an active member of the International Test Conference steering committee. Research interests: DFT, advanced fault models, defect distribution in Si. Contact: ron_press@mentor.com, 503-685-7954.

Arik Krantz is a DFT methodologist in the Technology Solutions Organization of Freescale, and has eight years of experience in DFT and test. He has a B.Sc. degree in computer engineering from Technion-Israel Institute of Technology. Research interests: DFT, test, power analysis, networking, and security. Contact: Arik@freescale.com, 972-9-952-2711.

Asher Berkovitz is leading the back end team in the CAD department of Freescale Israel, and has seven years of experience in back end design. Research interests: Power analysis, DFT, P&R, and timing flows. Contact: RM96518@freescale.com, 972-9-952-2727.

Cynthia Hao is a DFT Methodologist in the Technology Solutions Organization of Freescale. She has more than 12 years of experience in the semiconductor industry and five years of management roles at Freescale. Research interests: DFT and test. Contact: Pingli.Hao@freescale.com, 512-6-805-6679.

Giri Podichetty is a technical marketing engineer in the Silicon Test Solutions Division at Mentor Graphics. He has more than 20 years of ASIC design experience in most aspects of design implementation from inception to final tape-out. Giri received a bachelor’s degree in engineering from Teesside University in the United Kingdom. Contact: giri_podichetty@mentor.com.

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