While the word “ecosystem” is happily bantered about by major FPGA vendors, history would indicate that FPGA companies are less than perfect participants in the care and feeding of “ecosystems” to support their products. The turmoil associated with the love/hate, competitor/partner, customer/supplier relationships between FPGA companies and others providing various products and services to the FPGA community are well documented.
Commercial EDA companies are a perfect case-in-point. While trying to make a business creating and selling design tools to FPGA designers, they need to cooperate closely with FPGA companies in the creation of their tools and supporting libraries, and then they have to compete with those same FPGA companies who are providing competitive tools directly to their customers at virtually no cost.
EDA companies have always relied on two arguments to justify customers’ investments in their third-party tools instead of the FPGA vendors’ offerings – better tools and vendor independence. The “better tools” differentiator is a constant race – EDA companies have to sprint to keep their tools ahead of the FPGA vendors, and the FPGA companies are constantly catching up. Compounding that effect – when an EDA company introduces a new feature, it is never long before that same capability shows up in an FPGA vendor’s tool. We’re not talking about patent violations here – just a “fast follower” strategy on the part of FPGA companies trying to compete with each other by offering as close as possible to commercial-grade tools in their almost-free standard offerings. Nonetheless, top-flight EDA providers like Altium, Mentor Graphics, and Synplicity have managed to keep their offerings one (or three) steps ahead of the vendors’, keeping their tool businesses intact.
The second argument – “vendor independence” has always been on shaky ground. While it sounds nice in concept to have your designs and design tools easily retargetable from one vendor to another – say, if vendor “B” suddenly announces a newer, cheaper, faster part than the one you started with, that vision has never really been very practical. One of the biggest obstacles to vendor-independent design is IP. If you throw down some common peripheral like a PCI core (or these days, a microprocessor), you may save yourself a lot of design work, but you’ve just locked your design forever in the silicon of the vendor whose IP you chose. FPGA companies know this, and they invest a lot in building vast libraries of IP that they make available for a pittance.
Sometimes, this vendor-supplied IP is not easy to remove from your design once you’ve designed it in. For example, if you include a proprietary processor core in your FPGA design and then write a bunch of processor-specific software based on that architecture – it won’t be a trivial change to remove that processor and replace it with an alternative if you want to jump to a different FPGA supplier. The solution to this “sticky IP” problem is vendor-independent IP – the kind that people want to sell for money.
In the ASIC arena, commercial IP has been big business for a while now. Licensable IP can dramatically reduce design and verification cycles and can also significantly improve design parameters like power, performance, and cost. IP that has been engineered and proven over years of commercial use is almost always better than what your team will whip up in their spare time – particularly for non-differentiating functions such as standard interfaces. It is a rare product that beats out the competition because its USB interface is more elegant.
In FPGA, however, commercial IP has never really caught on. The “big and mostly free” libraries provided by the FPGA companies has dissuaded third-party investment in creating commercial IP targeted at FPGAs in two ways: First, IP companies don’t want to invest in developing a commercial IP product only to have the FPGA vendors release “free” versions of the same cores before they can recoup their investment. Second, the expectation of free IP has somewhat conditioned the FPGA market against paying a premium for high-quality design blocks.
This means that the “ecosystem” one would hope for in vendor-independent, high-performance tools and IP for FPGA design has never really matured. Although we may see a short-term win in this situation from the availability of low-cost tools and IP directly from FPGA companies, we lose in the long run because not much of the vast resources and expertise of commercial EDA and IP companies are applied to FPGA design. We are forced to rely much more heavily on the FPGA companies to develop this technology for us. Similarly, the FPGA companies are forced into a position where they have to develop most of the tools and IP themselves in order to maintain critical mass, and that additional cost is passed on to us in the form of higher prices for silicon.
This week, Synplicity announced that they have modified their highly-popular FPGA design tools to take advantage of the IP-XACT standard from the Spirit Consortium – providing a set of capabilities they call “ReadyIP”. ReadyIP is designed to provide easy access to a wide variety of conforming IP to designers and to provide a secure and convenient distribution, evaluation, and configuration mechanism for commercial IP vendors wanting to reach the FPGA market. This could be a turning point in the IP battle that will provide FPGA customers access to a broader range of vendor-independent IP and IP vendors a better means to make a profitable business on FPGA IP.
Of course, ready availability of pedestrian IP wouldn’t get our attention. Another library of multipliers, muxes, and MSI miscellany could hardly form the lynchpin of a new market. The key to the impact of Synplicity’s announcement is the availability of high-end flagship IP such as 32-bit processor cores, and that’s exactly what the company is bringing with this announcement. Founding partners involved in the initiative are ARM, CAST, Gaisler Research, and Tensilica. Tensilica is new on the FPGA scene, and they’re taking advantage of the Synplicity rollout to make their Diamond 106Micro 32-bit RISC processor available to FPGA designers with no license fee, provided your production volumes are less than 10,000 cumulative units. The 106Micro will join ARM’s Cortex-M1 as a technology-independent, FPGA-ready processor core migrating over from the ASIC world. Both companies apparently see the FPGA community as fertile ground for seeding future high-volume, fee-based adoption of their cores in the ASIC/SoC market and, additionally, as a way to expand the proliferation of software specific to their architecture.
Synplicity’s ReadyIP flow uses open IP encryption methodology to provide the IP vendor a range of options for allowing evaluation and adoption. IP vendors can distribute encrypted versions of their cores and select which capabilities potential licensees are allowed in evaluating – simulation, synthesis and timing, etc. The available options affect such things as visibility, technology targets, and hierarchy preservation.
In addition to support for IP encryption, Synplicity has added a new integrated IP assembly feature that allows drag-and-drop construction of FPGA-based systems using IP blocks. Synplicity has added “System Designer” to both its Synplify Pro and Synplify Premier tools that provide easy system-on-chip construction and configuration and support the “try before you buy” IP evaluation flow.
This announcement could very well signal the opening of floodgates of vendor-independent IP for FPGAs. For quite some time, ASIC IP vendors have been working to make their ASIC IP at least FPGA-compatible because of the large numbers of ASIC design teams that use FPGAs to verify and prototype their ASIC designs. A number of EDA and IP companies like ARM, Cadence, Mentor Graphics, and Synopsys (who recently announced plans to acquire Synplicity) are already heavily involved in the Spirit Consortium, so a wider range of interoperable IP and tools should be flowing into the FPGA world through conduits like Synplicity’s ReadyIP.
From our perspective, the continuing standardization of IP evaluation and delivery mechanisms is a win for everybody involved. Synplicity’s announcement may just bring the benefits of that reality to the FPGA community sooner rather than later.
