XMOS xCore-200 Wants to Replace Peripherals

Deterministic Processor an Alternative to Typical Code Drivers

by Jim Turley

Oftentimes, the decision comes down to “FPGA or ASIC.” But what if the decision was “FPGA or microprocessor?”

That’s essentially the value proposition from XMOS, the British microprocessor company that pitches its products not as alternatives to the usual rogues’ gallery of CPUs, but as an alternative to an FPGA.

And now that decision gets a little bit tougher.

You see, in the usual hardware/software partitioning that we’re all familiar with, you start out with fixed hardware resources (some combination of a CPU or MCU, some fixed logic, and maybe some programmable logic) and then you begin to apply software. Pretty standard, right?

 

Intel Plus Altera

What Would it Mean?

by Kevin Morris and Bruce Kleinman

There has been rampant speculation this week on rumors that Intel is in negotiations to buy Altera - in a deal that should be worth over ten billion, and which would be the largest acquisition in Intel’s history. While neither company is saying anything public yet, there is a substantial amount of information available from which to evaluate the potential impact of such a move and to speculate about the reasons behind it.

We actually predicted this eight months ago in our aptly-named article “When Intel Buys Altera” (subtle title, no?), and the arguments we made back then still apply today. But, with almost another year of progress under our collective belts, we should be able to raise the resolution on our crystal ball considerably. While there has been a considerable amount of press and analyst attention on these rumors, we think the analysts are largely off base. We’ll go into the problems with the analyst theories separately, but, for now, here is our take: 

Also - please note that there has not been any deal announced as of this writing. We are speculating here - caveat emptor.

 

It’s EUV Season Again

Spoiler: No, We’re Not There Yet

by Bryon Moyer

I know, I know, you’re all at the edge of your seats, wondering if it’s ok to start designing assuming EUV lithography. Actually… I suppose if it’s critical to you, you’ve already got inside tracks and you attend all the update sessions, so you’re probably already up to speed. But the rest of you are just dying to know, I’m sure.

SPIE Advanced Litho happened recently, and there are three larger stories to tell here, although, at present, unless something changes, it seems like only two of them will have an impact. Each of these stories corresponds to one of the potential purveyors of EUV lithography sources. We’ll close with other notes and players.

 

All Modules All the Time

Microchip Takes LoRa and Motion Detection by Storm

by Amelia Dalton

One of the biggest challenges in IoT communications is distance. In this week’s Fish Fry, we examine a new communications technology called LoRa. Tyler Smith (Microchip Technology) is here to tell us how it can be used, where it is best suited for implementation, and how LoRa could change the future of IoT communications. Also this week, we look into the details of a new motion detection module that packs a big ol’ punch by combining a powerful motion co-processor with 9-axis sensors (including an accelerometer, a magnetometer, and a gyroscope) all in an itty-bitty package.

 

TI MCU Goes 32-Bit

New MSP432 Family is ARM-Based… Of Course

by Jim Turley

Spring is sprung. The grass is riz. I wonder where the chips they is. – Justifiably Anonymous

Springtime means growth. Growth means change. Change means adjusting to new things.

For TI’s perennial MSP430 family of MCUs, today marks the start of a new season. A new branch on the family tree, if you will. For today, the MSP430 grows up – to 32 bits. It has reached that awkward adolescent stage where it has outgrown its toy box but isn’t quite ready for a desk job. It was time for a big change, a growth spurt, and that transition always comes at a price.

 

HLS is the New Black

Cadence Stratus Ushers In a New Era

by Kevin Morris

It’s been more than twenty years since I started working on high-level synthesis (HLS). You might say I’ve studied the topic a lot. For most of those two-plus decades, HLS has been widely considered the “design methodology of the future.” And there are those who have held onto the belief that it always will be.

For those of you not in tune with the terms, high-level synthesis is the automatic creation of hardware architectures from behavioral descriptions. At first, HLS was known as “behavioral synthesis.” But, after some early bad experiences, the EDA industry quietly shifted the name over to HLS - hoping that nobody would notice or have episodes of PTSD when confronted with the idea.

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