CEO For a Day

How Would You Save Some of the Industry’s Basket Cases?

by Jim Turley

You finally get the phone call. Bill Gates and Steve Ballmer are on speakerphone, calling you while you grill hot dogs in the backyard. Beer in one hand, BBQ tongs in the other (and Bluetooth headset in your ear), you shoot the breeze with your ol’ buddies Bill and Steve.

“So, [insert your name here], what’dya say? Do you want to come be the new CEO of Microsoft? Of course, you’d have to move to Redmond, but we could make that worth your while. Company car… big salary… corner office(s)… Do we have a deal?”

Would you take the job? In this scenario, Satya Nadella remains EVP of the company’s Cloud and Enterprise group, reporting to you. You would oversee all of Microsoft’s worldwide operations, controlling business strategy, technical development, licensing terms – you name it.

 

Toward Ten TeraFLOPS

Altera Kicks Up Floating Point

by Kevin Morris

The Cray-2, the world’s fastest computer until about 1990, was capable of almost 2 GigaFLOPS (Billion Floating Point Operations per Second) - at an inflation-adjusted price of over $30 million. A decade later, ASCI Red - selling for a cool $70 million or so - topped one teraFLOPS (Trillion Floating Point Operations per Second). The machine was twice as expensive, but the price per performance had dropped from ~$15M/GFLOPS (Cray) to ~$70K/GFLOPS (ASCI Red). That’s a shocking improvement. Moore’s Law would have us believe in a ~32x gain over the course of a decade, but real-world supercomputers delivered over 200x in just ten years. Take that, Dr Moore!

Sometime in 2015, according to Altera, we will have a single FPGA (yep, that’s right, one chip) - designed by Altera and manufactured by Intel - capable of approximately TEN teraFLOPS. Let’s do some math on that, shall we? We don’t know exactly what a Stratix 10 FPGA will cost, but it almost doesn’t matter. This device should put us in the realm of $1/GFLOPS. Or, compared to ASCI Red, an additional 70,000x improvement in cost per performance.

 

Programming QuickLogic’s Sensor Hub

Hardware from a Software Standpoint

by Bryon Moyer

Well, it seems to be sensor hub season. A couple of interesting things are brewing. One, in particular, is of strategic significance, and I’ll be writing that up once I get a chance to dig into some more details.

For today, we’re going to go tactical rather than strategic: we’re going to dig deeper into QuickLogic’s sensor hub solution. And we’re going to get our hands dirty. If you read my earlier piece on sensor hub partitioning, you’ll recall that QuickLogic has a rather intricate implementation that puts much of the sensor hub functionality in FPGA hardware using a combination of low-level software, state machines, and outright hardware. Their claim is that they can achieve the lowest power this way – lower than a more common microcontroller implementation.

 

When Eight Is Enough

Microchip's 8-bit Challenge

by Amelia Dalton

There is a common assumption that innovation cannot be inspired in the world of 8-bit microcontrollers. If that is the case, then why haven’t they disappeared like the telegraph or the 8-track tape? Perhaps it's because we still need them and sometimes they are just what the doctor (or engineer as the case may be) ordered. In this week’s Fish Fry, I check out some cool new 8-bit MCUs from Microchip Technology with Greg Robinson (VP - Microchip Technology) and we dive down into the guts of these new 8-bit masterpieces - from the intelligent analog features to the digital pin placement capabilities. Also this week, we investigate how Israeli start-up StoreDot plans to revolutionize battery technology. (Hint: It includes chemically synthesized bio-organic peptide molecules!)

 

Freescale Goes Nuts for ARM

New Kinetis Families and a Major Acquisition Equal 900+ Parts

by Jim Turley

They say change is good, so Freescale must be the best microprocessor company in the whole world.

What hasn’t this company done? It’s change its name, changed its processor architecture(s), changed its financial structure, changed its management (repeatedly), and totally reorganized its product lines, business units, and development structure. In between, I’m sure they’ve changed the office wallpaper and the filter in the break-room coffee maker. I remember sitting down to a meeting with some Freescale marketing types. They glanced across the table at my hand-scribbled org chart of their company and asked politely, “Could we have a copy of that, please?” Seems they were as confused about the company’s structure as I was.

 

Heartbleed: Serious Security Vulnerability

Serious Wake-up Call

by Bruce Kleinman, FSVadvisors, foreword by Kevin Morris

Imagine if you woke up one morning, and found out that Walmart was now selling a device for $5 that could easily and instantly open almost any deadbolt lock. That’s right - the kind of lock that is supposed to give “extra protection” to just about every door on earth. That’s the magnitude of security problem posed by the Heartbleed Bug.

Contributing columnist Bruce Kleinman wrote the first half of this article and posted it to his “From Silicon Valley” blog on April 6, 2014. The timing of the post was a remarkable coincidence: just 36 hours before the Heartbleed Bug started making headlines.

As the creators of technology, we engineers need to re-think our commitment to security and safety. The systems we design don’t just earn us money – they are often trusted to protect people’s lives, privacy, and assets. This is a solemn responsibility that is all too often overlooked or given short shrift in our ongoing race to get timing closure, first silicon, working prototypes, and volume shipments.

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