editor's blog
Subscribe Now

Faster NoC Tuning

In a sleepy little town of 4 or 5 houses, you can be pretty informal about how mail arrives at its destinations. People can come pick it up at the post office, or the postmaster can drop it off on the way home, or whatever works. But once you get too many houses, you have to get organized: create routes and schedules and hire delivery folks to handle deliveries in a more structured manner.

That’s what’s happened with SoCs: the ad-hoc interconnect schemes of yore are giving way to networks-on-chip (NoCs) so that the complex communication interplay between blocks can be carefully designed, managed, and tuned.

Which is good, except that a NoC is a complex animal, and, traditionally, it goes into the chip layout mix as part of the whole – it’s just another (complex) bit of IP. Layout affects performance, so tuning and closing the timing of a NoC in the middle of the rest of the layout would presumably be a difficult proposition. It also adds a significant burden to the EDA tools trying to manage the whole thing.

So Arteris has a proposal: segregate the NoC that from the rest of the circuit and optimize it independently. This relies on a layout that provides channels between IP instances where the NoC lines and circuits will be placed.

They describe a three-step process starting after initial layout. First, the NoC IP is isolated so that timing and routing can be optimized. In the second part, pipeline stages are automatically added (as they point out, you’ll never get from point A to point B across a 28-nm chip in one clock cycle). Finally, timing is closed using physical synthesis – which they claim can provide single-pass success.

FlexNoC_drawing.png 

This lets you optimize the NoC unburdened by the rest of the SoC, and it lets the EDA tools handle the rest of the SoC unburdened by the NoC. Arteris says that this divide-and-conquer approach gets you to tape-out faster than trying to do the whole thing at once.

You can read more in their announcement.

Leave a Reply

featured blogs
Mar 29, 2024
By Mark Williams, Sr Software Engineering Group Director Translator: Masaru Yasukawa 差動アンプはã1つの入力信号ではなく2つの入力信号間の差にゲインをé...
Mar 26, 2024
Learn how GPU acceleration impacts digital chip design implementation, expanding beyond chip simulation to fulfill compute demands of the RTL-to-GDSII process.The post Can GPUs Accelerate Digital Design Implementation? appeared first on Chip Design....
Mar 21, 2024
The awesome thing about these machines is that you are limited only by your imagination, and I've got a GREAT imagination....

featured video

We are Altera. We are for the innovators.

Sponsored by Intel

Today we embark on an exciting journey as we transition to Altera, an Intel Company. In a world of endless opportunities and challenges, we are here to provide the flexibility needed by our ecosystem of customers and partners to pioneer and accelerate innovation. As we leap into the future, we are committed to providing easy-to-design and deploy leadership programmable solutions to innovators to unlock extraordinary possibilities for everyone on the planet.

To learn more about Altera visit: http://intel.com/altera

featured chalk talk

Improving Chip to Chip Communication with I3C
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Amelia Dalton and Toby Sinkinson from Microchip explore the benefits of I3C. They also examine how I3C helps simplify sensor networks, provides standardization for commonly performed functions, and how you can get started using Microchips I3C modules in your next design.
Feb 19, 2024
5,475 views