editor's blog
Subscribe Now

Sensor Hub Power Drops Again

ArcticLink_3_S2_PR_Image_FINAL_cr.jpgQuickLogic is back, pushing power numbers down again. They’re now touting what they say is the lowest-power sensor hub, at 75 µW, with their ArcticLink 3 S2 LP.

You may recall that QuickLogic’s ArcticLink 3 is a “custom PLD,” if you like. It’s got an internal programmable fabric, plus hardened logic and a couple of processors. The solution, much of which comes pre-canned, is a combination of logic and state machine and multipliers and microcode, with a modicum of programmability. It’s a carefully crafted approach, as we discussed a while back.

QuickLogic has come back a couple of times with power reductions on their original device. I asked what changed in the S2 LP vs. the prior S2: process and design tweaks. There’s no functional difference. I asked if there was ever a reason to use the S2 instead of the S2 LP; their answer was, “Not really.” So it seems to be a story of “lower power for free.” How often do you get that?

Competitors will question how much processing this device will allow – it’s certain that there are other solutions – likely microcontroller-based – that could, with larger memories, handle more sophisticated algorithms – at the cost of higher power. PNI can probably squeeze more algorithm-per-microwatt than a generic microcontroller since their solutions are largely fixed. (Programmability costs…) But they’re still higher than 75 µW.

But much of that is conjecture and gut-feel on my part. Where the breaking point is for each of these architectures… well, I don’t know if anyone has a real answer to that. Almost makes you wish for some way of figuring out what can go into which device for how much power.

You can read more in QuickLogic’s announcement.

 

(Image courtesy QuickLogic)

Leave a Reply

featured blogs
Apr 19, 2024
Data type conversion is a crucial aspect of programming that helps you handle data across different data types seamlessly. The SKILL language supports several data types, including integer and floating-point numbers, character strings, arrays, and a highly flexible linked lis...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

OPTIGA™ TPM SLB 9672 and SLB 9673 RPI Evaluation Boards
Sponsored by Mouser Electronics and Infineon
Security is a critical design concern for most electronic designs today, but finding the right security solution for your next design can be a complicated and time-consuming process. In this episode of Chalk Talk, Amelia Dalton and Andreas Fuchs from Infineon investigate how Infineon’s OPTIGA trusted platform module can not only help solve your security design concerns but also speed up your design process as well.
Jun 26, 2023
33,858 views