editor's blog
Subscribe Now

Faster Extraction from Cadence

Cadence recently announced new extraction tools, claiming both greater speed (5x) and best-in-class accuracy for full-chip extraction. And what is it that lets them speed up without sacrificing results?

The answer is the same thing that has benefited so many EDA tools over the last few years: parallelism. Both within a box (multi-threading) and using multiple boxes (distributed computing). The tools can scale up to hundreds of CPUs, although they’re remaining mum on the details of how they did this…

They have two new tools:  a new random-walk field solver (Quantus FS) and the full-chip extraction tool (Quantus QRC). They say that the field solver is actually running around 20 times faster than their old one.

The field solver is much more detailed and accurate than the full-chip extraction tool. It’s intended for small circuits and high precision; its results are abstracted for use on a larger scale by the full-chip tool. That said, they claim good correlation between QRC and FS, so not much is lost in the abstraction.

They’ve also simplified the FinFET model, cutting the size of the circuit in half and increasing analysis speed by 2.5x.

While QRC is intended for the entire chip, it can also be used incrementally – in which case it can be three times again as fast. Both the Encounter digital implementation tool and their Tempus timing analysis tool can take advantage of this incremental capability to do real-time extraction as the tools make decisions. It’s also integrated into the Virtuoso analog/custom tool.

As to accuracy, they say they meet all of TSMC’s golden FinFET data, that they achieve consistent results with single- and multi-corner analysis, and that they’ve been certified by TSMC for the 16-nm node.

Their fundamental capabilities are summarized in the following figure, although this coverage is consistent with the prior tools.

QRC_functions_500.png

Image courtesy Cadence

You can read more in their announcement.

Leave a Reply

featured blogs
Nov 19, 2018
At the Linley Fall Processor Conference recently, the keynote on the second day was by Cliff Young of Google titled Codesign in Google TPUs: Inference, Training, Performance, and Scalability . The TPU is Google's Tensor Processing Unit. It is actually a family, since, as...
Nov 16, 2018
If you aren'€™t from the packaging world, then chances are likely you might think '€œpacking'€ refers to objects being placed in to a box instead of packaging integrated circuits (IC'€™s) on a substrate. Packaging has advanced since it began, and as with many areas i...
Nov 14, 2018
  People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...
Nov 13, 2018
Podcast Interview with the authors of The Hitchhikers Guide to PCB Design eBook by Mike Beutow with PCB Chat....