editor's blog
Subscribe Now

Improved FPGA Tool Results

A bit over a year ago, we looked at startup Plunify, who was marketing cloud-based FPGA tool instantiations. I talked to them again at the recent DAC, and they appear to be carrying out the typical modern startup roadmap, where you start with something, find out what people really do with it, and then use that information to drive new, and sometimes wholly different, products.

What they learned with their original offering was that the analytics module was really popular. So they figured out how to harness the information to help automate FPGA design optimization in the FPGA tools.

The result is called InTime, and it rides over the top of the Altera and Xilinx tools. It does a series of builds, watching the results, and then making recommendations to the designer as to which settings and constraints will provide the best results. Notably, it doesn’t touch the RTL, so this is about matching up the existing design with the tool in the most effective way.

This isn’t a typical design space exploration platform, which tends to have an element of random. This is a directed algorithm that looks at the results of the original full runs and then uses those analytics to refine the settings and constraints to achieve results that they claim to be 30-40% better than what design space exploration provides.

Not only does it improve the design at hand, but they say it can learn over time. If you’re using the cloud, then the global tool accumulates the learning, improving over time. One thing that’s changed from their original offering, however, is the cloud focus. While still available, too many companies are reluctant to go to the cloud, so they also support local instantiation. When implemented locally, the learning will accrue to the benefit of all local designs.

You can learn more in their recent announcement.

Leave a Reply

featured blogs
Jul 17, 2018
In the first installment, I wrote about why I had to visit Japan in 1983, and the semiconductor stuff I did there. Today, it's all the other stuff. Japanese Food When I went on this first trip to Japan, Japanese food was not common in the US (and had been non-existent in...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...