editor's blog
Subscribe Now

Synopsys’s IP Initiative

IP used to refer to hardware designs that could be purchased off the shelf. Actually, at first they were designs that wouldn’t really work for any real application without a consulting contract to adapt them. But, over time, “shrink wrapped” became more viable. The idea was to save design time.

That idea still holds, but we’ve replaced one problem – design of individual blocks – with another: assembling all of the IP blocks into a complete system. And these IP blocks are more than your grampa’s simple fast Fourier transform; these are typically complete protocols that need to run a software stack.

Once assembled, the system will run the system software that’s being written for the SoC in parallel with the hardware design –software that’s separate from, and likely makes use of, the shrink-wrapped protocol libraries that may accompany the hardware IP.

So the full project development process involves hardware designers getting hardware running – first in prototypes, then in silicon. Meanwhile, software guys are coding away, using both virtual prototypes of the hardware and, eventually, the hardware prototypes that the hardware buys built.

In order to accommodate this more complex flow, Synopsys has announced their IP Initiative. It involves a more holistic view of how IP is integrated into SoCs, and the idea is to make the IP and accompanying elements work out of the box so no time is wasted on things that have already been completed – all of the effort can go into integration.

The image below shows the bigger picture of what they’re trying to accomplish. It includes both existing elements (like the hardware IP) and new elements being released as of the announcement, like the prototyping kits.

Figure.png

The IP prototyping kits are intended for hardware engineers, and they include a working reference design out-of-the-box on a HAPS board. IP licencees will have access to the accompanying IP RTL. Meanwhile, the IP software development kits include tools and virtual platform models of the IP that, again, work out-of-the-box.

The final bit, customized IP subsystems, gets to the challenges of putting all of these pieces together and coaxing them to work. Individual IP blocks work out of the box, but assembling them into an SoC isn’t trivial. Synopsys offers services to help create subsystems out of blocks.

You can read more about their offering in their announcement.

Leave a Reply

featured blogs
Jul 20, 2018
https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market Thursday: Breakfast Bytes Guide...
Jul 19, 2018
In the footer of Samtec.com, we'€™ve always made it easy to contact us by phone, email, or live chat (even fax back in the day!). To continue to progress this theme, you'€™ll now find a new helpful tool in the footer area of Samtec.com. This tool will match you up with yo...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...