editor's blog
Subscribe Now

Power Bank SoCs

I ask a lot of stupid questions because usually they’re not stupid. Occasionally one is.

OK, maybe not outright stupid, but I certainly felt out of the loop. I was talking with Active-Semi about their new power bank management chips. But I tend to run my phones with minimal bells and whistles on. WiFi is typically off; GPS is often off. Bottom line: the charge on my phone can easily last a day, sometimes two.

So I hope I can be forgiven for not knowing in advance what a “power bank” was. I’ve never had a chance to need one. Apparently I’m not typical: Active-Semi’s Mark Cieri noted that it’s not unusual for smartphones to need a new charge after only 4 hours. Who knew… (Apparently everyone but me!)

Active-Semi has announced two new SoCs for managing these critters. As they describe it, the status quo requires separate components: a power path chip, a linear charger, a buck/boost regulator, and a microcontroller to manage it all.

Their solution is a single chip that integrates all of these capabilities together, including management and regulation. One version delivers 1 A; the other 2.1 A. The result: a noticeably (50%) smaller footprint.

Oh, and significantly less power draw: under 10 µA, vs. 45 – 100 µA for conventional circuits. So the manager won’t be siphoning off too much of the energy it’s supposed to be managing.

You can find out more in their announcement.

Leave a Reply

featured blogs
Jul 20, 2018
https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market Thursday: Breakfast Bytes Guide...
Jul 19, 2018
In the footer of Samtec.com, we'€™ve always made it easy to contact us by phone, email, or live chat (even fax back in the day!). To continue to progress this theme, you'€™ll now find a new helpful tool in the footer area of Samtec.com. This tool will match you up with yo...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...