SPICE is pretty fundamental to circuit design. That’s obvious for cell and custom designers; for you digital folks, you get exempted only because a cell designer already did the work for you. And, as with everything EDA, things are getting harder to compute with each process node.
Part of it is incremental. New nodes come with increasingly important parasitic modeling. That’s always been the case from generation to generation, not because of new parasitics, but because of old ones that used to be ignored that now mattered. But with FinFETs, you have those plus complex new parasitic relationships that have never been there before.
Cadence says that, despite the fact that the “H” in HSIM* stands for “hierarchical,” this hierarchy gets screwed up by the Rs and Cs. Lose the hierarchy and you lose the performance advantage it provides.
There’s another change that’s made life tougher for SPICE. In earlier days, performance could be increased by partitioning the job into channels, with PMOS transistors connected to VDD and NMOS to ground. But power gating has screwed that all up: those connections aren’t direct anymore because of the gates in the way. The power network had to be solved separately from the design, with the result munged back together at the end.
And so performance has suffered. Cadence’s latest SPICE XPS (eXtensive Partitioning Simulator) algorithms are said to use new partitioning algorithms that scale more linearly than their earlier exponential versions. Performance with power gating has returned to what it was in the old days before power gating. They’re touting a 10X improvement in speed, along with fewer required computing resources.
And how, you might ask, are they doing the partitioning now? I did ask. And they’re not saying.
Their current release is optimized for memory. Mixed signal designs will run, but not quite as fast; they’re anticipating that being optimized in the first half of 2014.
You can read more in their announcement.
*Edited to fix the error noted below…