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Interconnect @ 7 nm

IC interconnect is supposed to do two things: provided a path for electrons with as little resistance as possible and ensure that different paths don’t interact with each other. The first is about metal, the second about the dielectric between metal lines.

Copper is a good, low-resistance metal, but you can’t simply put copper on silicon or it can diffuse in. So you have to put down a barrier layer first, some sort of metal that will block the copper from contacting the silicon directly. Then you need a seed layer to enable the copper to adhere to the barrier and grow from there when deposited.

So far, we’ve been using Ta and TaN as barriers, about 16 nm of it. With a thick metal stack, that’s not an issue. The barrier itself may not have the lowest-possible resistance, but when it’s a small percentage of the stack, with copper making up the bulk, then, for the most part, you don’t notice.

Problem is, copper is getting thinner, and the barrier isn’t. This means that the resistance is going up as the percent of copper goes down. Which suggests the need for a new barrier that can be made thinner (putting off the day of reckoning).

As related in a discussion coincident with Imec’s Technology Forum and Semicon West, Imec has found that a 4-nm layer of Mn can reduce the resistance of 40-nm half-pitch lines by 45%, suggesting that this could be a good next step. It’s not a done deal yet, since they haven’t demonstrated reliability, nor have they completed the other duties needed to get a new material into the manufacturing flow; those efforts are underway.

Meanwhile, on the dielectric side of things, low-Κ dielectrics get their low Κ from the fact that they’re porous and have embedded carbon. The problem is, during an etch cycle, the etchant starts to invade the pores and remove the carbon. When done only on the fringes of a large expanse of oxide, that might not have a discernible effect. But on thin strips of oxide between metal lines, it essentially turns what are supposed to be low-Κ lines into normal-Κ lines.

In order to explore what might happen if the etch operation was done at very low temperatures, Imec did some experiments under cryogenic conditions. As expected, the ion mobility went down, slowing depletion, but a surprise effect occurred: some sort of barrier layer developed on the oxide, protecting it from the etchant. They’re not really sure what this barrier consists of.

They are also not sure what temperature enables the effect. If it truly requires cryogenic conditions, then it’s likely going to be too expensive to put into production. But if simply lowering the temperature to something more accessible can cause the effect, then we may have something interesting to pursue.

The thing is, Imec says that this is the only solution to the etch issue currently under study. So if it doesn’t work, then we’re back to square 1. Obviously, their fingers are crossed.

You can find out more about their metal announcement in one release and their dielectric announcement in another.

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