editor's blog
Subscribe Now

3D-IC Planning

During Cadence’s recent CDNlive event, I had a discussion with Kevin Rinebold to talk about 3D-IC planning and design. Actually, it’s more than that, covering all of the multi-die/package combinations like system-in-package (SiP), complex PC boards, and interposer-based solutions. The basic issue is that it’s becoming increasingly difficult to separate die design from board/package design; you may have to plan both together.

Said another way, what used to be board design duties have encroached on die design as packages have started to look more and more like micro-PCBs. The “lumpiness” of old-fashioned design is giving way to a more distributed approach as the “lumps” interact in non-lumpy ways.

Cadence’s approach splits the process in two: planning and implementation. Their focus during our discussion was the planning portion. Why split this part of the process out? Because it’s generally being done by the packaging people (“OSATs”), not the silicon people. So the OSATs will do high-level planning – akin to floorplanning on a die (and may actually involve floorplanning on a substrate).

They hand their results to the implementation folks via an abstract file and, possibly, some constraints to ensure that critical concerns will be properly addressed during design. The abstract file isn’t a view into a database; it is a one-off file, so if changes are made to the plan, new abstracts can (or should) be generated.

Cadence says the key to this is their OrbitIO tool, from their Sigrity group. It allows mechanical planning – things like ensuring that power and ground pins are located near their respective planes. They can also do some power IR drop analysis, although more complete electrical capabilities will come in the future.

There’s one other reason why the planning and implementation are done with completely different tools (mediated by the abstract file): OSATs tend to work on Windows machines, while designers tend to work on Linux machines. No, this is not an invitation to debate. (Oh, wait, Apple isn’t involved in this comparison… OK… never mind…)

Leave a Reply

featured blogs
Jul 20, 2018
https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market Thursday: Breakfast Bytes Guide...
Jul 19, 2018
In the footer of Samtec.com, we'€™ve always made it easy to contact us by phone, email, or live chat (even fax back in the day!). To continue to progress this theme, you'€™ll now find a new helpful tool in the footer area of Samtec.com. This tool will match you up with yo...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...