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The Challenges of Testing MEMS

Last month saw this year’s edition of the MEMS Test and Reliability conference. And there are clearly numerous issues to be addressed. To be clear, that’s not to say, for example, that there are inherent device reliability issues. It’s just that testing and measuring aren’t nearly as obvious for MEMS as they are for ICs.

Two issues in particular caught my eye. The first was the relationship between wafer test and final/packaged test. In the IC world, there are certainly things that you can’t test at the wafer level – true performance being one of them (because the wafer card probes are horrible for super-fast signaling). But things are even tougher with MEMS.

First off, a true test of a mechanical device means mechanical actuation to test the response. And each type of MEMS device has some sort of testing fixture to allow that. “Shakers” or other mechanical contraptions are used both for testing and calibration – when the devices are diced and packaged. But they don’t work for wafers. (I don’t know how much things have changed since I tried reliably aligning 84 probes – a lot at the time – onto pads, but at least then, once they were down, you didn’t even breathe much less shake the damn thing…)

So that means that either you can’t test it or you need some other way of calibrating it. In fact, designers include actuation mechanisms so that they can emulate physical actuation at the wafer level. Some level of calibration at wafer sort is important for final test correlation – which I’ll come back to in a sec.

But before we get to final test, there’s one other major limitation at wafer sort for many MEMS devices: they need an ASIC, and most ASICs are on a separate die. So wafer testing must proceed without that ASIC. That places some significant limitations on what can be done – especially if the ASIC helps clean up a noisy analog signal that will only be made worse by clunky wafer probes. And there’s no real solution to this one in the offing unless you can bring the CMOS and MEMS together – typically envisioned as monolithic integration.

InvenSense has an alternative, with their Nasiri technique. There the CMOS and MEMS are built on separate wafers, but the two wafers are then bonded face-to-face; the “handle” wafer that carries the MEMS devices is then etched back to expose the external connections on the CMOS wafer. So you end up with a wafer that can be probed, and it has both the ASIC and MEMS together. This allows them to test much more at wafer sort, eliminating the extra cost of packaging up and testing dice that will be thrown away.

The other major issue affects not just wafer and final testing, but also final board assembly. These are physical devices, and they respond to physical stresses, and each “situ” is different. During wafer sort, probes press vertically on the wafer. At final test, a test jig or handler somehow grabs the package (exactly how depends on the package type). That results in different stresses on the package, and, unfortunately, the die inside the package is not mechanically isolated from those stresses.

So, especially for any piezoelectrics, you may have a correlation issue between wafer sort and final test. That’s why getting some calibration information at wafer sort is important – that can be used to adjust data acquired at final test.

But that’s not the end of it: that device will eventually be soldered down onto a board or placed in a socket, both of which will place yet different stresses on the device. So the measurements taken at final test won’t necessarily correlate with final in situ measurements, were those to be taken.

And this one, at present, has no known good solution. These are some of the issues that motivate self-calibration, but that has yet to be developed as a commercial solution.

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