The use of photons as signal carriers has historically gone towards long-distance transport, either over the air (feels like waves more than photons) or within fiber. But the distances of interest have dropped dramatically, to the point where there are discussions of using silicon photonics even for on-chip signaling.
In a conversation at Semicon West with imec’s Ludo Deferm, we discussed their current work. At this point, and for at least 10 years out, he doesn’t see CMOS and photonics co-existing on the same wafer. The bottleneck right now isn’t on-chip; it’s chip-to-chip. 40-60 Gb/s internally is fine for now. Which suggests the use of photonics in a separate chip in, for example, a 3D-IC stack or on an interposer: one for routing signals between the chips in the stack.
That photonic chip would be made with the same equipment as a CMOS chip – a specific goal of the imec work in commercializing silicon photonics, but it starts with a different wafer: SOI, with a thinner silicon layer than you would have in a typical CMOS wafer, and with that thickness (or thinness) tightly controlled to reduce optical losses.
You can read more about imec’s progress in their recent announcement.