editor's blog
Subscribe Now

450 In Belgium

Changing wafer size is a big deal. You can kiss all your old equipment good-bye and usher in a whole new suite. So what happens when you’re planning to use that wafer size for a new technology node? You really don’t want to have to have two sets of production equipment, one for each side of the wafer-size shift. But it would also be rough to develop a new wafer size at the same time as developing a new technology node. That’s risk upon risk.

I talked with Ludo Deferm at Semicon West, where 450-mm was all the rage. But this excitement is clearly about things yet to come: there’s not much equipment available yet; only one item – KLA-Tencor’s blank wafer metrology unit – has been announced. And that just ensures that you’re starting with a good blank wafer. The rest is yet to come.

And imec sees 14 nm being the starting node for 450 mm. But the 450-mm R&D facility that imec just got government help for isn’t going to be started until 2014 – you can do the math on when it’s likely to be up and running. So if we had to wait for that before we could develop 14-nm technology, we’d be a long ways away.

As it is, imec is doing 14-nm development work on 300-mm wafers – it’s just that that equipment won’t be used for production. It’s just to get the process itself up. Clearly it will take some freshening up on the new 450-mm equipment when it’s ready. By that time, they’ll already be developing the 10-nm node.

As a curious side fact, he noted that a 200-mm cleanroom is actually more expensive to build than the 450-mm facility. That’s because, back then, the whole room had to be clean. Now everything is sealed in FOUPs, so, while it’s probably not a good idea to be tracking mud into the room or smoking, the level of cleanliness in the room is actually less than it used to be. Inside the equipment, however, there’s little forgiveness for the slightest intruder.

More on the Flemish investment can be found here

Leave a Reply

featured blogs
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...
Apr 16, 2024
Learn what IR Drop is, explore the chip design tools and techniques involved in power network analysis, and see how it accelerates the IC design flow.The post Leveraging Early Power Network Analysis to Accelerate Chip Design appeared first on Chip Design....
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

PIC32CX-BZ2 and WBZ451 Multi-Protocol Wireless MCU Family
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Amelia Dalton and Shishir Malav from Microchip explore the benefits of the PIC32CX-BZ2 and WBZ45 Multi-protocol Wireless MCU Family and how it can make IoT design easier than ever before. They investigate the components included in this multi-protocol wireless MCU family, the details of the software architecture included in this solution, and how you can utilize these MCUs in your next design.
May 4, 2023
39,987 views