editor's blog
Subscribe Now

A New 3D IC Approach

While 3D ICs have been sexy for a while, actually building them has been a bit more of a stately process than simply talking about them. The details house numerous devils that must be worked out in order for the process to be manufacturable.

One way that TSMC is approaching it is through what they call CoWoS: Chip on Wafer on Substrate. This is a 2.5-D process, really: the multiple dice are mounted on a silicon interposer. The catch is that this happens while the interposer wafer is still whole. This allows known-good dice to be mounted and tested together using a wafer methodology instead of assembling onto interposers that have already been diced up.

Once the completed stack is diced up, they are mounted on the package substrate, and packaging proceeds as normal.

The issues driving this approach are concerns that potential customers of 3D IC processing have ostensibly had about having multiple players in the process, with wafers from different sources being shuttled to packaging houses for further assembly. Some companies apparently view such a process as risky. Using this process, TSMC controls and does everything up to and including getting the structures onto the package substrate (making me wonder whether it was really customers or simply TSMC who was concerned).

Cadence’s role was in the front-end design portion of the project. You have multiple dice that have to know something about each other in order for the required signals to meet properly, and in order for traces that start on one die and end on another, passing through the interposer en route, to be modeled properly. This can have a non-trivial effect on the design workflow, since changes on one die may have implications for another die, and such events must be communicated. It’s still a partially-manual process, but they’re laying down the infrastructure for this paradigm change.

Modeling of the TSVs themselves (which communicate from the interposer redistribution layer down to the package substrate) is also new.

Cadence expects TSMC to go into full production on this in 2013; right now, come customers are working with it in a pre-production state.

You can find more info in Cadence’s release

Leave a Reply

featured blogs
Nov 19, 2018
At the Linley Fall Processor Conference recently, the keynote on the second day was by Cliff Young of Google titled Codesign in Google TPUs: Inference, Training, Performance, and Scalability . The TPU is Google's Tensor Processing Unit. It is actually a family, since, as...
Nov 16, 2018
If you aren'€™t from the packaging world, then chances are likely you might think '€œpacking'€ refers to objects being placed in to a box instead of packaging integrated circuits (IC'€™s) on a substrate. Packaging has advanced since it began, and as with many areas i...
Nov 14, 2018
  People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...
Nov 13, 2018
Podcast Interview with the authors of The Hitchhikers Guide to PCB Design eBook by Mike Beutow with PCB Chat....