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FPGA Prototype Debug Access

When tracing events on any kind of system, it’s always faster to go local: the farther away the data has to go, the slower it goes. Which is why FPGAs are nice in that their internal memory can be used as a trace buffer, allowing really fast capture.

But that also means that you have to have that memory available. Synopsys has announced a daughter card for their HAPS prototype systems that allows fast capture to an off-chip memory. It uses their custom HAPS-TRAK connector. The clock can run over 200 MHz, but it’s used to sample a system clock of up to 60 MHz. It works in conjunction with their RTL debugger, Identify (of Synplicity pedigree).

Some FPGA resource is still needed – roughly 500 LUTs for the SRAM controller and 2-4 LUTs per watchpoint – but the need for FPGA trace buffer memory is eliminated.

The connector that this debug card plugs into is also used for a variety of other I/O adapter cards – which, at first blush, would seem to be a problem since you can’t stack daughter cards. If there were only one, then you’d have to choose between I/O and debug – not a fun choice. But, in fact, there are 6 or 7 such connectors per FPGA (and multiple FPGAs per board), so any such tradeoff is much less likely.

After the trace capture, the daughter card can be offloaded via JTAG, which does take a couple minutes.

More detail in their release

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