editor's blog
Subscribe Now

Full Networking Offload

Eight months ago, Atheros (now part of Qualcomm) released a WiFi offload chip, their AR4100. It’s part of a push to enable internet-of-things applications with good-to-go 802.11b/g/n connectivity; it includes everything except the antenna. (And NVM, which is cheaper to implement with a second chip.)

They just announced some upgrades to that product, but they’ve also launched a new chip, the 4100P, which adds full networking offload. The 4100P has UDP and IPv4/v6 stacks, freeing up 60-100K of microcontroller NVM since the microcontroller no longer has to worry about this.

Meanwhile, they’ve cut down both the code store (formerly around 38K, now 24-25K) and the working memory requirements (was 11K, is now 8K) for the 4100 drivers.

While the difference between just 802.11 and UDP and IP is mostly handled in software, there apparently are some OTP settings on the chip that are different between the 4100 and the 4100P; the latter is somewhat more than simply the former with different software.

You can find more info in their release

Leave a Reply

featured blogs
Apr 23, 2024
The automotive industry's transformation from a primarily mechanical domain to a highly technological one is remarkable. Once considered mere vehicles, cars are now advanced computers on wheels, embodying the shift from roaring engines to the quiet hum of processors due ...
Apr 22, 2024
Learn what gate-all-around (GAA) transistors are, explore the switch from fin field-effect transistors (FinFETs), and see the impact on SoC design & EDA tools.The post What You Need to Know About Gate-All-Around Designs appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Optimize Performance: RF Solutions from PCB to Antenna
Sponsored by Mouser Electronics and Amphenol
RF is a ubiquitous design element found in a large variety of electronic designs today. In this episode of Chalk Talk, Amelia Dalton and Rahul Rajan from Amphenol RF discuss how you can optimize your RF performance through each step of the signal chain. They examine how you can utilize Amphenol’s RF wide range of connectors including solutions for PCBs, board to board RF connectivity, board to panel and more!
May 25, 2023
37,471 views