editor's blog
Subscribe Now

Yield Correlations Get Continued Focus

Yield enhancement has never been easy, but it just keeps getting harder as process technologies get more complex. Figuring out where you’re losing dice actually takes a lot of number crunching and correlation between widely disparate types of data.

First you’ve got your basic yield information as embodied in a wafer map. But one wafer doesn’t a trend make; it takes lots to develop the statistics to suggest where systematic problems might lie.

Isolating a particular type of failure, you can then do things like figure out what possible causes might be – which requires both information on the failure mode and access to the design – and a further narrowing down based on the physical layout of the design, which requires a picture of the layout.

All under the guidance of a skilled engineer, of course.

Mentor announced what they called “DFM-aware diagnosis-driven yield analysis.” As you might guess, the focus here is on DFM issues. Unlike strict DRC rules that must pass, DFM rules are more “suggestions.” You may well end up with some that didn’t pass. But if you get systematic yield loss, the obvious question becomes, was that because of some of the DFM rules we blew off?

The Tessent DFM-aware analysis looks for correlations between failures and failed DFM rules. If you find some, you can decide whether to make changes so that they pass. On the other hand, there may be none that correlate: you may actually decide that a new DFM rule is required to fix the observed failures. So you can also test with the new DFM rule to see if there’s a correlation between that and the failure before adding the rule.

Synopsys, meanwhile, announced enhanced yield diagnostics and, in particular, tools to improve memory yields through similar kinds of correlation techniques. They show a loop between the design, from which vectors are generated and sent to the tester, and from which results are gathered. Those results are combined with the original design information in their STAR Silicon Debugger, from which maps of failing bits as well as the physical coordinates of those failures can be derived. From there, and engineer can look for actual failure mechanisms.

More info in the Mentor and Synopsys press releases…

Leave a Reply

featured blogs
Sep 24, 2018
One of the biggest events in the FPGA/SoC ecosystem is the annual Xilinx Developers Forum (XDF). XDF connects software developers and system designers to the deep expertise of Xilinx engineers, partners, and industry leaders. XDF takes place in three locations this year.  Sa...
Sep 24, 2018
For the second year, the Electronic Design Process Symposium (EDPS) took place in Milpitas, having been at Monterey for many years. This was apparently the 25th year EDPS has run. I find EDPS to be a fascinating conference, and I think it is a shame that more people don'...
Sep 21, 2018
  FPGA luminary David Laws has just published a well-researched blog on the Computer History Museum'€™s Web site titled '€œWho invented the Microprocessor?'€ If you'€™re wildly waving your raised hand right now, going '€œOoo, Ooo, Ooo, Call on me!'€ to get ...
Sep 20, 2018
Last week, NVIDIA announced the release of the Jetson Xavier developer kit. The Jetson Xavier, which was developed in OrCAD, is designed to help developers prototype with robots, drones, and other......