editor's blog
Subscribe to EE Journal Daily Newsletter

HLS from Scratch

On the heels of the announcement of an entirely new analog design tool suite comes something else surprising. And I can’t quite figure it out.

I received an “announcement” of a new HLS (i.e., nominally, a C-to-VHDL) tool called HercuLeS. Except that the announcement didn’t read like a commercial launch: it read more like a note to friends and colleagues. It was written by Nikolaos Kavvadian, who describes himself in his email signature as “Lecturer, Research scientist, Hardware developer, Ph.D., M.Sc., B.Sc.”

I followed up with him to clarify whether this was a research effort or a commercial launch. He confirmed that this was developed separately from his academic work, and that it is a commercial, not an academic, venture. But apparently it’s not really commercialized yet: you can get to it online, but there’s a web interface that’s going to be released in October. At that point, the tool will still be available for free for limited programs; the pricing for full-on use hasn’t been set yet.

He doesn’t view HercuLeS competing specifically with the usual EDA suspects (which is mostly Catapult C, since Cadence and Synopsys deal with SystemC, not ANSI C). He sees some niche markets that they’ll be focusing on in Q4, including select supercomputing applications and the FPGA+µP (Altera/Intel, Xilinx/ARM) space.

I asked about quality of results (QoR): it’s relatively straightforward to come up with a model for converting software to hardware; the hard part is doing that efficiently, and the incumbents have years of accumulated QoR improvements under their belts. This sets a really high bar for newcomers to be taken seriously. Dr. Kavvadian acknowledged the importance of QoR, asserting that one main contributor to QoR is the intermediate representation (IR) used.

And this seems to be a key to this technology: it’s focused on GIMPLE, a Gnu set of IRs that have front ends to various languages, and NAC, a low-level language they have defined. The language (ANSI C in this case) is mapped to GIMPLE, and they then map that to NAC. NAC can be extended to provide improved mappings to hardware as experience builds. He sees this, along with optimized implementation of black boxes and their model of computation, as the crucial element.

The IR also unlocks something else they have their eye on: possible support of Python and Go or other languages that can be mapped to GIMPLE. Such users are another possible niche market for them.

All in all, I’m not quite sure what to make of this. It’s clearly very engineering driven, and the “launch” lacks many of the standard business trappings – which may not be a bad thing. Just a confusing thing. The business model – or at least the pricing – still aren’t set, so it’s almost like we’re watching this evolve.

We’ll keep an eye to see what happens. Meanwhile you can check here for more information.

Leave a Reply

featured blogs
May 22, 2017
As part of the RISC-V workshop, Dave Patterson gave a talk on computer architecture. He recently retired from UC Berkeley, and in another sense it was a career retrospective. He did let drop that he is working with Google so his retirement doesn’t seem to involve the tra...
May 19, 2017
Chris Shelly, Samtec’s RF/SI Modeling Engineer, walks us through another 12G SDI product demonstration from NAB 2017. This demonstration showcases the Samtec BNC Edge Mount connector used in the Fidus® Gearbox+™ and the Phabrix® QX UHDTV 12G SDI generator/ana...