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Scenarios – Certain and Less So

Feeling somehow less worthy in the shadow of the passing of Bob Pease… (with no offense intended towards Docea…)

I spent a few minutes with Docea at DAC a couple weeks ago. You may recall their Aceplorer product dealing with both power and thermal analysis. Two things caught my eye, one of which is a new feature, the other something they’re working on.

The new feature is scenario generation. This is particularly applicable to multi-mode designs, where different modes are exercised as different scenarios. Marketing might refer to them as high-level use cases. Not only is this intended for what-if analysis and architecture optimization, but the results can also be fed to virtual platforms for downstream evaluation.

The thing they’re working on is 3D IC modeling (who isnt’?). This is actually something they announced last year in association with French research group CEA-Leti. I learned a bit more about what it is they’re paying particular attention to.

While they can see their way clear on power modeling for 3D ICs, they’re tinkering a bit more with the thermal side to see if their approach can work. They don’t use a full solver for thermal analysis; they use thermal RC network models, and extending that to stacked dice and all of the bits and bobs that may end up in the sandwich for thermal or redistribution purposes makes it something less than a chip shot.

More info on their latest announcement (plus now-expired discussion of their DAC demos) in their release

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