editor's blog
Subscribe Now

Custom Chip Planning

Digital designers have had semi-automated design flows for a long time; custom and analog designers, not so much.

Pulsic recently announced that they’re taking some of the custom EDA technology they’ve had for ten years, combining it with new technology, and integrating it into a flow as their Pulsic Planning Solution. I got a chance to talk to them about it at DAC.

Their solution consists of four components:

  • a hierarchical floorplanner, the Unity Chip Planner;
  • a power grid planner, the Unity Power Planner, which can handle multiple domains;
  • a tool for planning bus routing and layer, the Unity Bus Planner;
  • and a tool for any signal that’s not a bus, the Unity Signal Planner.

They tie into other tools via OpenAccess. They claim to address pretty much any part of the design flow except taking RTL and turning it into GDS-II. They can feed parasitics and signal integrity info into the planning tools to refine the results. The planning process is iterative; each refinement will feed either a better estimate or an actual value to update the overall plan.

They claim that this is the only planning solution specifically targeted for the custom digital or analog space: ASIC tools can sometimes fake it, but don’t do so well with some of the aspect ratios and other idiosyncrasies of custom design.

More info in their recent release

Leave a Reply

featured blogs
Jul 20, 2018
https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market Thursday: Breakfast Bytes Guide...
Jul 19, 2018
In the footer of Samtec.com, we'€™ve always made it easy to contact us by phone, email, or live chat (even fax back in the day!). To continue to progress this theme, you'€™ll now find a new helpful tool in the footer area of Samtec.com. This tool will match you up with yo...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...